All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
CY7C1352G
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:B]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and
DQP[A:B] (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the Write operation is controlled by
BW
[A:B]
signals. The CY7C1352G provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
[A:B]
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Because the CY7C1352G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP
[A:B]
inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
[A:B]
are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
BW
[A:B]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Document #: 38-05514 Rev. *A
Page 4 of 13
PRELIMINARY
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
CY7C1352G
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SNOOZE MODE
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BW
x
X
X
X
X
X
X
L
L
H
H
X
X
OE
X
X
L
L
H
H
X
X
X
X
X
X
CEN
L
L
L
L
L
L
L
L
L
L
H
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
DQ
tri-state
tri-state
Data Out (Q)
Data Out (Q)
tri-state
tri-state
Data In (D)
Data In (D)
tri-state
tri-state
–
tri-state
Notes:
2. X=”Don't Care.” H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables active. BWX = L signifies at least one Byte Write Select is active, BWX = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
[A:B]
, and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:B]
= tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
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