CQV8110 · CQV8100 · CQV890 · CQV880 · CQV870 · CQV860 · CQV850 · CQV840
ChannelQ
TM
3.3 Volt Synchronous 8 Channel Queue
Memory Configuration
131,072 x 40
65,536 x 40
32,768 x 40
16,384 x 40
8,192 x 40
4,096 x 40
2,048 x 40
1,024 x 40
Device
CQV8110
CQV8100
CQV890
CQV880
CQV870
CQV860
CQV850
CQV840
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single device solution providing complete data queuing and switching functions (up to 166 MHz)
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
5-bit wide data channels, up to sixteen channels per chip (80 bits total)
Reconfigurable data switching supporting channel unicast, multicast and broadcast
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
Parallel/Serial programming of PRAF and PRAE offset values
Programmable 8-bit or 10-bit parallel programming modes for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
PRAF and PRAE operates in either synchronous or asynchronous modes
Individual synchronous channel output enable signals controlling tri-state data output drivers
Asynchronous device output enable signals controlling tri-state data output drivers
Data retransmission with programmable zero or normal latency modes
Switching management
Available package: 144 - pin Plastic Thin Quad Flat Pack (TQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s ChannelQ
TM
product family represents the next generation bandwidth management solutions by providing advanced data
queuing and switching functions within a single chip. System designers can take full advantage of the flexible data switching
functions offered by the ChannelQ products while maintaining access to all the advanced features available in HBA’s existing
FlexQ
TM
family, such as programmable FIFO status flags, programmable data access timing (First-Word-Fall-Through and
Standard modes), data retransmission with programmable latency mode, and tri-state output data drivers.
3C040B
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Page 1 of 1
CQV8110 · CQV8100 · CQV890 · CQV880 · CQV870 · CQV860 · CQV850 · CQV840
ChannelQ
Product Description (Continued)
TM
The channel switching capability provides a means for unicast / multicast / broadcast of individual channel data when they are
written to the internal FIFO memory. The configuration of the channel switch can be reprogrammed on the fly. Because the
device combines data queuing and switching into a single chip, it in effect implements a switching fabric with input data queuing,
which has a broad range of applications in data communication. For detailed information on programming and using the
ChannelQ
TM
devices, please refer to the ChannelQ Application Note.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select and synchronous channel
output enables are also available to control the state of data output drivers, allowing multiple ChannelQ devices to share a single
output data bus. Independent Write and Read controls provide rate-matching capability.
Master Reset clears all previously programmed configurations by providing a low pulse on
MRST
pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting
REN
. This feature is useful when implementing
depth expansion functions. In this mode, DRDY and
QRDY
are used instead of
FULL
and EMPTY respectively.
In Standard mode, always assert
REN
for a read operation.
FULL
and EMPTY are used instead of DRDY and
QRDY
respectively.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0
th
(Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit
operation.
ChannelQ devices have low power consumption, hence minimizing system power requirements. In addition, industry standard
144 - pin Plastic TQFP is offered to save system board space.
These devices are ideal for applications such as data communication, telecommunication, test equipment, network switching, etc.
3C040B
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Page 2 of 2
CQV8110 · CQV8100 · CQV890 · CQV880 · CQV870 · CQV860 · CQV850 · CQV840
ChannelQ
TM
Programming Modes
Channel In
0
1
2
Channels
8
3
4
5
6
7
Channel Out
0
1
2
3
4
5
6
7
Channels
8
Output Channel
Channel Source
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Figure 1. 8x5-to-8x5 ChannelQ Configured in Unicast Mode
Channel In
0
1
2
Channels
8
3
4
5
6
7
Channel Out
0
1
2
3
4
5
6
7
8
Channels
Output Channel
Channel Source
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
Figure 2. 8x5-to-8x5 ChannelQ Configured in Broadcast Mode
3C040B
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Page 3 of 3
CQV8110 · CQV8100 · CQV890 · CQV880 · CQV870 · CQV860 · CQV850 · CQV840
ChannelQ
Channel In
0
1
2
Channels
8
3
4
5
6
7
Channel Out
0
1
2
3
4
5
6
7
8
Channels
TM
Output Channel
Channel Source
7
7
6
6
5
7
4
6
3
3
2
2
1
3
0
3
Figure 3. 8x5-to-8x5 ChannelQ Configured in Multicast Mode
Channel In
0
1
2
Channels
8
3
4
5
6
7
Channel Out
0
1
2
3
4
5
6
7
8
Channels
Output Channel
Channel Source
7
1
6
0
5
5
4
4
3
7
2
6
1
3
0
2
Figure 4. 8x5-to-8x5 ChannelQ Configured as a 4x10-to-4x10 Switch in Switching Mode
3C040B
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Page 4 of 4
CQV8110 · CQV8100 · CQV890 · CQV880 · CQV870 · CQV860 · CQV850 · CQV840
ChannelQ
Block Diagram of Single Channel Queue
131,072 x 40 / 65,536 x 40 / 32,768 x 40 / 16,384 x 40 / 8,192 x 40 / 4,096 x 40 / 2,048 x 40 / 1,024 x 40
TM
PARTIAL RESET (PRST )
MASTER RESET (MRST)
WRITE CLOCK (WCLK)
WRITE ENABLE ( WEN )
SWITCHING CONTROL REGISTER
WRITE ENABLE (
AWEN
)
LOAD ( LOAD
)
DATA IN (D
39 - 0
)
SERIAL DATA ENABLE ( SDEN )
FIRST WORD FALL THROUGH/SERIAL
DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
(FULL /
DRDY
)
PROGRAMMABLE
ALMOST-FULL ( PRAF)
READ CLOCK (RCLK)
READ ENABLE ( REN)
SWITCHING CONTROL REGISTER
READ ENABLE (
AREN
)
OUTPUT ENABLE ( OE)
DATA OUT (Q
39 - 0
)
RETRANSMIT ( RET)
EMPTY FLAG / OUTPUT READY
( EMPTY/
QRDY
)
PROGRAMMABLE ALMOST-EMPTY
(
PRAE
)
HALF-FULL FLAG (
HALF
)
INTERSPERSED/NON-INTERSPERSED
PARITY (IPAR)
CQV8110
CQV8100
CQV890
CQV880
CQV870
CQV860
CQV850
CQV840
Figure 5. Single Device Configuration Signal Flow Diagram
3C040B
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JULY 2002
Page 5 of 5
RF/Wirelessly
京公网安备 11010802033920号
EEWORLD
