A54SX32A-TQG144M datasheet, PDF

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A54SX32A-TQG144M: Descriptionfpga - field programmable gate array 32k system gates; CategoryProgrammable logic devices Programmable logic; File Size437KB，50 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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A54SX32A-TQG144M Overview

fpga - field programmable gate array 32k system gates

A54SX32A-TQG144M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	1.40 MM, TQFP-144
Reach Compliance Code	compliant
Other features	32000 TYPICAL GATES AVAILABLE
maximum clock frequency	206.9 MHz
Combined latency of CLB-Max	1.2 ns
JESD-30 code	S-PQFP-G144
JESD-609 code	e3
length	20 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2880
Equivalent number of gates	48000
Number of entries	113
Number of logical units	2880
Output times	113
Number of terminals	144
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2880 CLBS, 48000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2.5,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	20 mm

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v2.0

HiRel SX-A Family FPGAs

Features and Benefits

Leading Edge Performance

•

215 MHz System Performance (Military Temperature)

5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

240 MHz Internal Performance (Military Temperature)

•

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and Design

Theft

Cold-Sparing Capability

Individual Output Slew Rate Control

QML Certified Devices

100% Military Temperature Tested (–55°C to +125°C)

33 MHz PCI Compliant

CPLD and FPGA Integration

Single-Chip Solution

Configurable I/O Support for 3.3 V/5 V PCI, LVTTL,

and TTL

Configurable Weak Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power-Up

Up to 100% Resource Utilization and 100% Pin

Locking

2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Very Low Power Consumption

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary-Scan Testing in Compliance with IEEE

1149.1 (JTAG)

A54SX32A

32,000

48,000

2,880

1,800

1,080

1,980

228

Yes

5.3 ns

0 ns

Std, –1

84, 208, 256

A54SX72A

72,000

108,000

6,036

4,024

2,012

4,024

213

Yes

6.7 ns

0 ns

Std, –1

208, 256

Specifications

•

48,000 to 108,000 Available System Gates

Up to 228 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

0.25/0.22 µ CMOS Process Technology

Features

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (no sequencing required

for supply voltages)

Class B Level Devices

Three Standard Hermetic Package Options

•

Product Profile

Device

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

Maximum User I/Os

Global Clocks

Quadrant Clocks

Boundary-Scan Testing

3.3 V / 5 V PCI

Clock-to-Out

Input Set-Up (External)

Speed Grades

Package (by Pin Count)

CQFP

N o ve m b e r 2 0 0 6

See the Actel website for the latest version of the datasheet.

HiRel SX-A Family FPGAs

Table of Contents

General Description

QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

HiRel SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Detailed Specifications

2.5 V/3.3 V/5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

5 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

3.3 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

HiRel SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Package Pin Assignments

84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

International Traffic in Arms Regulations (ITAR) and Export Administration

Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

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