DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
Flash Disk with MLC NAND and M-Systems’ x2 Technology
Data Sheet, November 2005
Highlights
DiskOnChip G4 is M-Systems' 4
th
generation of
the DiskOnChip family of products. Based on
Multi-Level Cell (MLC) NAND, utilizing
Toshiba’s 90nm MLC NAND Large Block
flash technology and x2 technology from M-
Systems, it is one of the industry’s most
efficient storage solutions. MLC NAND flash
technology provides the smallest die size by
storing 2 bits of information in a single memory
cell. x2 technology enables MLC NAND to
achieve highly reliable, high-performance data
and code storage with a specially designed error
detection and correction mechanism, optimized
file management, and proprietary algorithms for
enhanced performance.
Further cost benefits derive from the
cost-effective architecture of DiskOnChip G4,
which includes a boot block that can replace
expensive NOR flash, and incorporates both the
flash array and an embedded thin controller in a
single die.
DiskOnChip G4 provides:
Flash disk for both code and data storage
Low voltage: 1.8V core and I/O
Hardware protection and security-enabling
features
High capacity: single die - 1Gb (128MB),
dual die - 2Gb (256MB)
Device cascade capacity: up to 4Gb
(512MB)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
69-ball FBGA 9x12 mm package
Enhanced performance by implementation
of:
DMA support
MultiBurst operation
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) tailored for MLC NAND flash
technology
Maximized flash endurance with TrueFFS
®
6.3.2 (and higher)
Support for major operating systems (OSs),
including Symbian OS, Microsoft Windows
Mobile, Palm OS, Nucleus, Linux, OSE,
Windows CE, and more.
Compatible with major CPUs, including
TI OMAP, TI DBB, Intel XScale, Infinion,
EGold and SGold, ADI 652x, Freescale
MX, and Qualcomm MSMxxxx.
1
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
Performance
Boot Capability
MultiBurst read: 15 MB/sec
Sustained read: 9 MB/sec
Sustained write: 2.4 MB/sec
Access time:
Normal: 33 nsec
Protection & Security-Enabling Features
16-byte Unique Identification (UID)
number
16KByte user-controlled One Time
Programmable (OTP) area
Two configurable hardware-protected
partitions for data and code:
Read-only mode
Write-only mode
One-Time Write mode (ROM-like)
partition
Protection key and LOCK# signal
Sticky Lock (SLOCK) to lock boot
partition
Protected Bad Block Table
Reliability and Data Integrity
2KB Programmable Boot Block with XIP
capability to replace boot NOR
Download Engine (DE) for automatic
download of boot code from Programmable
Boot Block
Asynchronous Boot mode to boot from
ARM-based CPUs, e.g. XScale, TI OMAP,
Freescale MX without the need for external
glue logic
Virtual and Paged RAM boot modes.Enable
booting from DiskOnChip under Secure
Boot platforms
Exceptional boot performance with
MultiBurst operation and DMA support
enhanced by external clock
Hardware Compatibility
Hardware- and software-driven, on-the-fly
EDC and ECC algorithms
4-bit Error Detection Code/Error Correction
Code (EDC/ECC), based on a patented
combination of BCH and Hamming code
algorithms, tailored for MLC NAND flash
technology
Guaranteed data integrity after power
failure
Transparent bad-block management
Dynamic and static wear-leveling
Configurable interface: simple NOR-like or
multiplexed address/data interface
CPU compatibility, including:
ARM-based CPUs
Texas Instruments OMAP, DBB
Intel XScale PXAxxx family
Infinion xGold family
Analog Devices (ADI) AD652x
family
Freescale MX family
Zoran ER4525
Renesas SH mobile
Qualcomm MSMxxxx
AMD Alchemy
Motorola PowerPC™ MPC8xx
Hitachi SuperH™ SH-x
Supports 8-, 16- and 32-bit architectures
2
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
TrueFFS
®
Software
Full hard-disk read/write emulation for
transparent file system management
Patented TrueFFS
Flash file system management
Automatic block management
Data management to maximize the
limit of typical flash life expectancy
Dynamic virtual mapping
Dynamic and static wear-leveling
Programming, duplicating, testing and
debugging tools available in source code
Operating Environment
Power Requirements
Operating voltage
Core, I/O: 1.65 to 1.95V
Current Consumption
Active mode:
Read 4.2mA
Program 7.4mA
Erase 7.4mA
Deep Power-Down mode:
10
µA
(1Gb/128MB)
20
µA
(2Gb/256MB)
Capacity and Packaging
Wide OS support, including:
Symbian OS
Microsoft Windows Mobile
Palm OS
Nucleus
Windows CE
Linux
OSE
VxWorks
TrueFFS Software Development Kit (SDK)
for quick and easy support for proprietary
OSs, or OS-less environment
TrueFFS Boot Software Development Kit
(BDK)
128MB (1Gb) capacity (single die):
Device cascading option for up to
four devices (4Gb)
69-ball FBGA package:
9x12x1.2 mm (width x length x
height)
Ballout compatible with
DiskOnChip G3/P3, G3/P3 LP and
H1 FBGA products
256MB (2Gb) capacity (dual die):
Device cascading option for up to
two devices (4Gb)
69-ball FBGA package:
9x12x1.4 mm (width x length x
height)
Ballout compatible with
DiskOnChip G3/P3, G3/P3 LP, H1
and, H3 FBGA products
3
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
R
EVISION
H
ISTORY
Doc. No
92-DT-0305-00
Revision
0.1
0.2
Date
March 2005
October 2005
Description
Preliminary version
Device ball number was reduced
from 115 to 69 balls (only not
connected balls were reduced).
Updated mechanical dimensions.
Updated Ordering Information.
92-DS-1105-00
0.3
November
Updated electrical information
Reference
-
Section 2
Section 10.4
Section 11
-
4
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
T
ABLE OF
C
ONTENTS
1. Introduction ............................................................................................................................... 9
2. Product Overview .................................................................................................................... 10
2.1
2.2
Product Description .......................................................................................................... 10
Standard Interface ............................................................................................................ 11
2.2.1
2.2.2
2.2.3
Ball Diagrams ..................................................................................................................... 11
System Interface ................................................................................................................ 12
Signal Description .............................................................................................................. 13
Ball Diagram ....................................................................................................................... 15
System Interface ................................................................................................................ 16
Signal Description .............................................................................................................. 17
2.3
Multiplexed Interface ........................................................................................................ 15
2.3.1
2.3.2
2.3.3
3. Theory of Operation ................................................................................................................ 19
3.1
3.2
Overview........................................................................................................................... 19
System Interface............................................................................................................... 20
3.2.1
3.2.2
Standard (NOR-Like) Interface........................................................................................... 20
Multiplexed Interface .......................................................................................................... 20
3.3
3.4
Configuration Interface ..................................................................................................... 20
Protection and Security-Enabling Features ...................................................................... 21
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Read/Write Protection ........................................................................................................ 21
Unique Identification (UID) Number ................................................................................... 21
One-Time Programmable (OTP) Area ............................................................................... 21
One-Time Write (ROM-Like) Partition ................................................................................ 22
Sticky Lock (SLOCK).......................................................................................................... 22
3.5
3.6
3.7
3.8
3.9
4.1
4.2
4.3
Programmable Boot Block with eXecute In Place (XIP) Functionality.............................. 22
Download Engine (DE) ..................................................................................................... 22
Error Detection Code/Error Correction Code (EDC/ECC) ................................................ 23
Control and Status............................................................................................................ 23
Flash Architecture............................................................................................................. 23
MultiBurst Operation......................................................................................................... 25
DMA Operation................................................................................................................. 28
Combined MultiBurst Mode and DMA Operation ............................................................. 29
4. x2 Technology ......................................................................................................................... 25
5. Hardware Protection ............................................................................................................... 30
5
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00
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