EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

251R15S3R9AV6U

Description
Ceramic Capacitor, Multilayer, Ceramic, 250V, 1.2821% +Tol, 1.2821% -Tol, NP0, -/+30ppm/Cel TC, 0.0000039uF, 0805,
CategoryPassive components    capacitor   
File Size752KB,12 Pages
ManufacturerJohanson Technology
Websitehttp://www.johansontechnology.com
Environmental Compliance
Download Datasheet Parametric View All

251R15S3R9AV6U Overview

Ceramic Capacitor, Multilayer, Ceramic, 250V, 1.2821% +Tol, 1.2821% -Tol, NP0, -/+30ppm/Cel TC, 0.0000039uF, 0805,

251R15S3R9AV6U Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid968339673
package instruction, 0805
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL8.1
capacitance0.0000039 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high1.02 mm
JESD-609 codee3
length2.03 mm
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance1.2821%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package formSMT
method of packingTR, EMBOSSED PLASTIC, 13 INCH
positive tolerance1.2821%
Rated (DC) voltage (URdc)250 V
size code0805
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient30ppm/Cel ppm/°C
Terminal surfaceTin (Sn) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
width1.27 mm
[RVB2601 Creative Application Development] 3. RGB three-color breathing light of RVB2601
[i=s]This post was last edited by kit7828 on 2022-3-10 14:00[/i]There is a ch2601_rgb_marquee_demo in the routine of Pingtou Ge, which is a demo to realize the three-color marquee effect of RGB LED la...
kit7828 XuanTie RISC-V Activity Zone
C6000 DSP Architecture
The high-performance C6000 DSP architecture has 8 parallel functional units, 2 groups of registers, separate program and data storage; 256-bit instruction fetch package, which can fetch 8 32-bit instr...
Jacktang Microcontroller MCU
Several classic FPGA verification books
SystemVerilog is a hardware description and verification language (HDVL). It is based on the IEEE1364-2001 Verilog hardware description language (HDL) and has been extended to include C language data ...
arui1999 Download Centre
FPGA learning experience - matrix keyboard
...
至芯科技FPGA大牛 FPGA/CPLD
Welcome the moderator "天意无罪" to take office~~
I'm glad that another netizen has joined the EEWorld moderator team~Here is the new moderator information: Username: God is innocent Responsible section: Comprehensive technical exchange Personal intr...
okhxyyo Integrated technical exchanges
Task stack overflow detection mechanism in FreeRTOS
In FreeRTOS, each task has its own stack, the size of which is determined by the function parameters of the xTaskCreate function when the task is created.However, when the stack space used by a task e...
MamoYU Real-time operating system RTOS

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号