®
X40020, X40021
Data Sheet
May 17, 2006
FN8112.1
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—V
TRIP2
programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor two voltages or detect power fail
• Battery switch backup
• V
OUT
: 5mA to 50mA from V
CC
; 250µA from V
BATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA battery current in backup mode
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• Monitor voltages: 5V to 1.6V
• Memory security
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
X40020, X40021
Standard V
TRIP1
Level Standard V
TRIP2
, Level Suffix
4.6V (±1%)
2.9V(±1.7%)
-A
4.6V (±1%)
2.6V (±2%)
-B
2.9V(±1.7%)
1.6V (±3%)
-C
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40020 combines power-on reset control, watch-
dog timer, supply voltage supervision, and secondary
supervision, and manual reset, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
+
V2 Monitor
Logic
-
V
OUT
V
TRIP2
V2FAIL
SDA
WP
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
Watchdog
and
Reset Logic
V
OUT
WDO
MR
RESET
X40020
RESET
X40021
SCL
V
OUT
V
CC
(V1MON)
+
V
CC
Monitor
Logic
-
V
TRIP1
Power-on,
Manual Reset
Low Voltage
Reset
Generation
BATT-ON
V
OUT
V
BATT
System
Battery
Switch
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40020, 40021
Ordering Information
PART
NUMBER*
WITH RESET
X40020S14-C
PART
MARKING
X40020S C
PART
NUMBER*
WITH RESET
X40021S14-C
PART
MARKING
X40021S C
MONITORED
V
CC
SUPPLIES
1.6 to 3.6
V
TRIP1
RANGE
(mV)
2.9 ±50
V
TRIP2
RANGE
(mV)
1.6 ±50
TEMP.
RANGE (°C)
0 to 70
PACKAGE
PKG.
DWG. #
14 Ld SOIC (150 mil) MDP0027
X40020S14I-C X40020S IC X40021S14I-C X40021S IC
X40020V14-C
X4002 0VC
X40021V14-C
X4002 1VC
-40 to +85 14 Ld SOIC (150 mil) MDP0027
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
M14.173
X40020V14I-C X4002 0VIC X40021V14I-C X4002 1VIC
X40020S14-B
X40020S B
X40021S14-B
X40021S B
2.6 to 5.5
4.6 ±50
2.6 ±50
-40 to +85 14 Ld TSSOP
(4.4mm)
0 to 70
0 to 70
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020S14Z-B X40020S ZB X40021S14Z-B X40021S ZB
(Note)
(Note)
X40020S14I-B
X40020S IB
X40021S14I-B
X40021S IB
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
0 to 70
0 to 70
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
X40020S14IZ-B X40020S ZIB X40021S14IZ-B X40021S ZIB
(Note)
(Note)
X40020V14-B
X4002 0VB
X40021V14-B
X4002 1VB
X40020V14Z-B X4002 0VZB X40021V14Z-B X4002 1VZB
(Note)
(Note)
X40020V14I-B
X4002 0VIB
X40021V14I-B
X4002 1VIB
-40 to +85 14 Ld TSSOP
(4.4mm)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
2.9 to 5.5
2.9 ±50
0 to 70
0 to 70
X40020V14IZ-B X4002 0VZIB X40021V14IZ-B X4002 1VZIB
(Note)
(Note)
X40020S14-A
X40020S A
X40021S14-A
X40021S A
14 Ld SOIC (150 mil) MDP0027
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020S14Z-A X40020S ZA X40021S14Z-A X40021S ZA
(Note)
(Note)
X40020S14I-A
X40020S IA
X40021S14I-A
X40021S IA
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
0 to 70
0 to 70
14 Ld TSSOP
(4.4mm)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
M14.173
X40020S14IZ-A X40020S ZIA X40021S14IZ-A X40021S ZIA
(Note)
(Note)
X40020V14-A
X4002 0VA
X40021V14-A
X4002 1VA
X40020V14Z-A X4002 0VZA X40021V14Z-A X4002 1VZA
(Note)
(Note)
X40020V14I-A
X4002 0VIA
X40021V14I-A
X4002 1VIA
-40 to +85 14 Ld TSSOP
(4.4mm)
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
X40020V14IZ-A X4002 0VZIA X40021V14IZ-A X4002 1VZIA
(Note)
(Note)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8112.1
May 17, 2006
X40020, 40021
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
TRIP1
point.
RESET/RESET is active until V
CC
returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V
CC
with V
BATT
input
and connects V
OUT
to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
PIN CONFIGURATION
X40020
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
BATT-ON
V
OUT
V
BATT
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V
SS
X40021
14-Pin SOIC, TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
BATT-ON
V
OUT
V
BATT
WP
SCL
SDA
50mA from V
CC
to 250µA from V
BATT
. The device only
switches to V
BATT
when V
CC
drops below the low V
CC
voltage threshold and V
BATT
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
PIN DESCRIPTION
Pin
1
2
Name
V2FAIL
V2MON
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when
not used.
Early Low V
CC
Detect.
This open drain output signal goes LOW when
V
CC
< V
TRIP1
.
When
V
CC
> V
TRIP1
, this pin is pulled high with the use of an external pull up resistor.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
PURST
thereafter. It has an internal pull up
resistor.
RESET Output.
(X40021) This open drain pin is an active LOW output which goes LOW whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
RESET Output.
(X40020) This pin is an active HIGH open drain output which goes HIGH whenever
V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and
for t
PURST
thereafter.
3
FN8112.1
May 17, 2006
3
4
5
LOWLINE
WDO
MR
6
RESET/
RESET
X40020, 40021
PIN DESCRIPTION
(Continued)
Pin
7
8
Name
V
SS
SDA
Ground
Function
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10MΩ typical)
Battery Supply Voltage.
This input provides a backup supply in the event of a failure of the
primary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not
used, connect V
BATT
to ground.
Output Voltage. (V)
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
then V
OUT
= V
CC
if V
CC
> V
BATT
+ 0.03V
else V
OUT
= V
BATT
(ie if V
CC
< V
BATT
– 0.03V)
Note:
There is hysteresis around V
BATT
± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to V
OUT
to ensure stability.
Battery On.
This CMOS output goes HIGH when the V
OUT
switches to V
BATT
and goes LOW when
V
OUT
switches to V
CC
. It is used to drive an external PNP pass transistor when V
CC
= V
OUT
and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to the V
OUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
9
10
11
SCL
WP
V
BATT
12
V
OUT
13
BATT-ON
14
V
CC
Supply Voltage
4
FN8112.1
May 17, 2006
X40020, 40021
PRINCIPLES OF OPERATION
Power-on Reset
Applying power to the X40020/21 activates a Power-
on Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V
CC
exceeds the device V
TRIP1
threshold value
for t
PURST
(selectable) the circuit releases the RESET
(X40021) and RESET (X40020) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40020
System
Reset
RESET
MR
Manual
Reset
X40021
Unreg.
Supply
5V
Reg
3V
Reg
V
CC
RESET
V2MON
V2FAIL
Notice:
No external components required to monitor two voltages.
System
Reset
Low Voltage V2 Monitoring
The X40020/21 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
TRIP2
. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V2FAIL signal remains active until the V
CC
drops below 1V (V
CC
falling). It also remains active until
V2MON returns and exceeds V
TRIP2
.
V2MON voltage monitor is powered by V
OUT.
If V
CC
and V
BATT
go away, V2MON cannot be monitored.
Figure 2. Two Uses of Multiple Voltage Monitoring
V
OUT
X40020
Unreg.
Supply
R
R
5V
Reg
V
CC
RESET
V2MON
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
V
OUT
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
t
PURST
or till the push-button is released and for t
PURST
thereafter. A weak pull up resistor is connected to the
MR pin.
Low Voltage V1 Monitoring
During operation, the X40020/21 monitors the V
CC
level and asserts RESET if supply voltage falls below
a preset minimum V
TRIP1
. The RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The V1FAIL signal remains active
until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP1
for
t
PURST
.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. A standard
read or write sequence to any slave address byte
restarts the watchdog timer and prevents the WDO sig-
nal to go active. A minimum sequence to reset the
watchdog timer requires four microprocessor instructions
namely, a Start, Clock Low, Clock High and Stop. The
state of two nonvolatile control bits in the Status Register
determine the watchdog timer period. The microproces-
sor can change these watchdog bits by writing to the
X40020/21 control register (also refer to page 21).
5
FN8112.1
May 17, 2006
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