AM29LV002BB-90FI datasheet, PDF

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AM29LV002BB-90FI: DescriptionFlash, 256KX8, 90ns, PDSO40, REVERSE, MO-142CD, TSOP-40; Categorystorage storage; File Size730KB，39 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29LV002BB-90FI Overview

Flash, 256KX8, 90ns, PDSO40, REVERSE, MO-142CD, TSOP-40

AM29LV002BB-90FI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	TSOP1
package instruction	TSOP1-R, TSSOP40,.8,20
Contacts	40
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	90 ns
Other features	MINIMUM 1000K WRITE CYCLES; 20 YEAR DATA RETENTION
startup block	BOTTOM
command user interface	YES
Data polling	YES
Data retention time - minimum	20
JESD-30 code	R-PDSO-G40
JESD-609 code	e0
length	18.4 mm
memory density	2097152 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1,2,1,3
Number of terminals	40
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1-R
Encapsulate equivalent code	TSSOP40,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
reverse pinout	YES
Maximum seat height	1.2 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	10 mm
Base Number Matches	1

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Am29LV002B

2 Megabit (256 K x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29LV002 device

High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

Ultra low power consumption (typical values at 5

MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyte sectors

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that

sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Mode Program Command

— Reduces overall programming time when issuing

multiple program command sequences

Top or bottom boot block configurations

available

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

Minimum 1,000,000 write cycle guarantee per

sector

20-year data retention at 125°C

— Reliable operation for the life of the system

Package option

— 40-pin TSOP

Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

21520

Rev:

Amendment/+1

Issue Date:

November 13, 2000

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29LV002B Device Bus Operations ................................ 8

Reading Toggle Bits DQ6/DQ2 ............................................... 19

Figure 6. Toggle Bit Algorithm ........................................................ 20

DQ5: Exceeded Timing Limits ................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Table 6. Write Operation Status..................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative Overshoot Waveform ...................... 22

Figure 8. Maximum Positive Overshoot Waveform ........................ 22

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 8

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ............................................................. 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode ................................................................ 9

Table 2. Am29LV002BT Top Boot Block Sector Address Table..... 10

Table 3. Am29LV002BB Bottom Boot Block Sector Address Table 10

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 24

Figure 10. Typical I

CC1

vs. Frequency ........................................... 24

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Test Setup ..................................................................... 25

Table 7. Test Specifications ........................................................... 25

Key to Switching Waveforms . . . . . . . . . . . . . . . 25

Figure 12. Input Waveforms and Measurement Levels ................. 25

Autoselect Mode ..................................................................... 10

Table 4. Am29LV002B Autoselect Codes (High Voltage Method).. 10

Sector Protection/Unprotection ............................................... 11

Temporary Sector Unprotect .................................................. 11

Hardware Data Protection ...................................................... 11

Figure 1. Temporary Sector Unprotect Operation ...........................11

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Operations .................................................................... 26

Figure 13. Read Operations Timings ............................................. 26

Hardware Reset (RESET#) .................................................... 27

Figure 14. RESET# Timings .......................................................... 27

Low V

Write Inhibit .............................................................. 11

Write Pulse “Glitch” Protection ............................................... 11

Logical Inhibit .......................................................................... 11

Power-Up Write Inhibit ............................................................ 11

Figure 2. In-System Sector Protect/Unprotect Algorithms ...............12

Erase/Program Operations ..................................................... 28

Figure 15. Program Operation Timings .......................................... 29

Figure 16. Chip/Sector Erase Operation Timings .......................... 30

Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31

Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31

Figure 19. DQ2 vs. DQ6 ................................................................. 32

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13

Reset Command ..................................................................... 13

Autoselect Command Sequence ............................................ 13

Byte Program Command Sequence ....................................... 13

Unlock Bypass Command Sequence ..................................... 14

Chip Erase Command Sequence ........................................... 14

Figure 3. Program Operation ..........................................................14

Temporary Sector Unprotect .................................................. 32

Figure 20. Temporary Sector Unprotect Timing Diagram .............. 32

Figure 21. Sector Protect/Unprotect Timing Diagram .................... 33

Alternate CE# Controlled Erase/Program Operations ............ 34

Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35

Sector Erase Command Sequence ........................................ 15

Erase Suspend/Erase Resume Commands ........................... 15

Figure 4. Erase Operation ...............................................................16

Command Definitions ............................................................. 17

Table 5. Am29LV002B Command Definitions................................. 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling ................................................................. 18

Figure 5. Data# Polling Algorithm ...................................................18

RY/BY#: Ready/Busy# ........................................................... 19

DQ6: Toggle Bit I .................................................................... 19

DQ2: Toggle Bit II ................................................................... 19

Erase and Programming Performance . . . . . . . 36

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 36

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 36

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37

TS 040—40-Pin Standard TSOP* .......................................... 37

TSR040—40-Pin Reverse TSOP ........................................... 38

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision A (January 1998) ..................................................... 39

Revision B (June 1998) .......................................................... 39

Revision B+1 (August 1998) ................................................... 39

Revision C (January 1999) ..................................................... 39

Revision D (November 18, 1999) ........................................... 39

Revision D+1 (November 13, 2000) ....................................... 39

Am29LV002B

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