PRA182C2-361KDPNT datasheet, PDF

PRA182C2-361KDPNT: DescriptionArray/Network Resistor, Bussed, Thin Film, 0.2W, 361000ohm, 150V, 0.5% +/-Tol, -10,10ppm/Cel, 1412,; CategoryPassive components The resistor; File Size102KB，5 Pages; ManufacturerVishay; Websitehttp://www.vishay.com; Environmental Compliance

Download Datasheet Parametric View All

PRA182C2-361KDPNT Overview

Array/Network Resistor, Bussed, Thin Film, 0.2W, 361000ohm, 150V, 0.5% +/-Tol, -10,10ppm/Cel, 1412,

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	983572613
package instruction	SMT, 1412
Reach Compliance Code	compliant
Country Of Origin	France
ECCN code	EAR99
YTEOL	7.2
Other features	ANTI-SULFUR, HIGH PRECISION
structure	Rectangular
Component power consumption	0.2 W
The first element resistor	361000 Ω
JESD-609 code	e2
Installation features	SURFACE MOUNT
Network Type	BUSSED
Number of components	2
Number of functions	1
Number of terminals	3
Maximum operating temperature	155 °C
Minimum operating temperature	-55 °C
Package height	0.5 mm
Package length	3.65 mm
Package form	SMT
Package width	3.06 mm
method of packing	TR
Rated power dissipation(P)	0.2 W
Rated temperature	70 °C
resistance	361000 Ω
Resistor type	ARRAY/NETWORK RESISTOR
Second/last element resistor	361000 Ω
size code	1412
surface mount	YES
technology	THIN FILM
Temperature Coefficient	10 ppm/°C
Temperature coefficient tracking	2 ppm/°C
Terminal surface	Tin/Silver (Sn/Ag) - with Nickel (Ni) barrier
Terminal shape	WRAPAROUND
Tolerance	0.5%
Operating Voltage	150 V

After allegro finishes drawing the PCB, I want to change the drawing size: After drawing the PCB with Allegro, I want to change the drawing size. After changing it in the design parameter editor, the drawing does not feel smaller, but the components and frames on the drawing...; shijizai stm32/stm8

Where does the DC bias at the output of the op amp in the figure below come from?: The figure below is an inverting adder, which uses the LM741CN integrated operational amplifier. The test results in the figure show that the amplification relationship conforms to the theoretical val...; 寅子敬 Analog electronics

Is this understanding of variable types correct?: Is this understanding of variable types correct?...; QWE4562009 MCU

DE1SOC transfers the available memory address in demo2_axi_app in BMP: [i=s]This post was last edited by cashong on 2020-2-24 17:40[/i]In the training material, in the bmp example in the advanced example, the function implemented is mainly that FPGA writes RGB to DDR3 on...; cashong Altera SoC

Share a cost-effective headset: [i=s]This post was last edited by ccmj4708 on 2020-4-22 22:14[/i]Recently I found a pair of cost-effective headphones on Mobao. The price is very good, only 8.88 yuan. After receiving the goods, I lis...; ccmj4708 Talking

Program file does not exist problem occurs in ON Semiconductor IDE: [i=s]This post was last edited by xujinxi on 2021-4-18 07:21[/i]When compiling the official example, the debug download failed, and the prompt is as follows. Has anyone encountered the same problem?In...; xujinxi onsemi and Avnet IoT Innovation Design Competition

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components