INTEGRATED CIRCUITS
DATA SHEET
TDA1312A; TDA1312AT
Stereo continuous calibration
DAC (CC-DAC)
Preliminary specification
File under Integrated Circuits, IC01
July 1993
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
FEATURES
•
8
×
oversampling (simultaneous input) possible
•
Voltage output
•
Space saving package SO8 or DIL8
•
Low power consumption
•
Wide dynamic range (16-bit resolution)
•
Continuous Calibration (CC) concept
•
Easy application:
– single 4 to 5.5 V rail supply
– output current and bias current are proportional to the
supply voltage
– integrated current-to-voltage converter
•
Internal bias current ensures maximum dynamic range
•
Wide operating temperature range (−40
°C
to
+
85
°C)
•
Compatible with most current Japanese input formats:
time multiplexed, two's complement and TTL
•
No zero-crossing distortion
•
Cost efficient.
ORDERING INFORMATION
TDA1312A; TDA1312AT
GENERAL DESCRIPTION
The TDA1312A; 1312AT is a voltage driven D/A converter
and is a device of a new generation of digital-to-analog
converters which embodies the innovative technique of
Continuous Calibration (CC). The largest bit-currents are
repeatedly generated by one single current reference
source. This duplication is based upon an internal charge
storage principle having an accuracy insensitive to ageing,
temperature matching and process variations.
The TDA1312A; 1312AT is fabricated in a 1.0
µm
CMOS
process and features an extremely low power dissipation,
small package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the CC-DAC is eminently
suitable for use in (portable) digital audio equipment.
PACKAGE
EXTENDED TYPE NUMBER
PINS
TDA1312A
(1)
TDA1312AT
(2)
Notes
1. SOT97-1; 1996 August 14.
2. SOT96-1; 1996 August 14.
8
8
PIN POSITION
DIL
SO8
MATERIAL
plastic
plastic
CODE
SOT97DE
SOT96AG
July 1993
2
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
V
FS
(THD+N)/S
PARAMETER
supply voltage
supply current
full scale output voltage
V
DD
= 5 V; at code 0000H
V
DD
= 5 V
CONDITIONS
TDA1312A; TDA1312AT
MIN.
4
−
1.8
−
−
−
−
−
−
86
−
−
−
−
5
TYP.
3.4
2.0
−68
0.04
−30
3
−33
2
92
0.2
−
−
±400
MAX.
5.5
6.0
2.2
−63
0.07
−24
6
−
−
−
−
18.4
18.4
−
V
UNIT
mA
V
dB
%
dB
%
dB
%
dB
µs
Mbits/s
MHz
ppm
total harmonic distortion plus at 0 dB signal level
noise
at
−60
dB signal level
at
−60
dB signal level;
A-weighted
S/N
t
CS
BR
f
BCK
TC
FS
signal-to-noise ratio at
bipolar zero
current settling time to
±1
LSB
input bit rate at data input
clock frequency at clock
input
full scale temperature
coefficient at analog
outputs (I
OL
; I
OR
)
operating ambient
temperature
total power dissipation
A-weighted; at code 0000H
T
amb
P
tot
−40
V
DD
= 5 V; at code 0000H
−
−
17
+85
30
°C
mW
July 1993
3
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July 1993
handbook, full pagewidth
Philips Semiconductors
Stereo continuous calibration
DAC (CC-DAC)
LEFT INPUT REGISTER
LEFT OUTPUT REGISTER
VOL
6
I/V
IOL
11-BIT
PASSIVE
DIVIDER
32 (5-BIT)
CALIBRATED
CURRENT
SOURCES
1 CALIBRATED
SPARE SOURCE
LEFT BIT SWITCHES
RIGHT INPUT REGISTER
RIGHT OUTPUT REGISTER
7
RIGHT BIT SWITCHES
I/V
IOR
32 (5-BIT)
CALIBRATED
CURRENT
SOURCES
1 CALIBRATED
SPARE SOURCE
11-BIT
PASSIVE
DIVIDER
VOR
4
BCK
DATAR
DATAL
WS
1
2
3
8
CONTROL
AND
TIMING
REFERENCE
SOURCE
TDA1312A
TDA1312AT
4
C2
5
VDD
TDA1312A; TDA1312AT
GND
100 nF
MGE225
Preliminary specification
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
PINNING
SYMBOL
BCK
DATAR
DATAL
GND
V
DD
V
OL
V
OR
WS
TDA1312A; TDA1312AT
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
bit clock input
right data input
left data input
ground
positive supply voltage
left channel output
right channel output
word select input
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The TDA1312A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs.4
and 5.
Data is placed in the right and left input registers (see
Fig.1). The data in the input registers is simultaneously
latched in the output registers which control the bit
switches.
An internal offset voltage V
OFF
is added to the full scale
output voltage V
FS
; V
OFF
and V
FS
are proportional to V
DD
:
Where V
DD1
/V
DD2
= V
FS1
/V
FS2
= V
OFF1
/V
OFF2
.
handbook, halfpage
BCK
DATAR
DATAL
GND
1
2
8
7
WS
VOR
VOL
VDD
TDA1312
3
TDA1312AT
6
4
MGE224
5
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage V
gs
on the
intrinsic gate-source capacitance C
gs
of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
ref
,
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage V
gs
of M1 is
not changed because the charge on C
gs
is preserved.
Therefore, the drain current of M1 will still be equal to I
REF
and this exact duplicate of I
REF
is now available at the OUT
terminal.
The 32 current sources and the spare current source of the
TDA1312A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
July 1993
5
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