DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Rev. 01 — 27 November 2008
Product data sheet
1. General description
The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog
Converter (DAC), optimized for high dynamic performance with low power dissipation.
Supporting an update rate of up to 125 Msps, the DAC1201D125 is suitable for Direct IF
applications.
Separate write inputs allow data to be written to the two DAC ports independently of one
another. Two separate clocks control the update rate of each DAC port.
The DAC1201D125 can interface two separate data ports or one single interleaved
high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its
original I and Q data and latched. The I and Q data is then converted by the two DACs and
updated at half the input data rate.
Each DAC port has a high-impedance differential current output, suitable for both
single-ended and differential analog output configurations.
The DAC1201D125 is pin compatible with the AD9765, DAC2902 and DAC5662.
2. Features
I
I
I
I
Typical 185 mW power dissipation
16 mW power-down
SFDR: 81 dBc; f
o
= 1 MHz; f
s
= 52 Msps
SFDR: 78 dBc; f
o
= 10.4 MHz;
f
s
= 78 Msps
I
1.8 V, 3.3 V and 5 V compatible digital
I
SFDR: 74 dBc; f
o
= 1 MHz;
inputs
f
s
= 52 Msps;
−12
dBFS
I
Internal and external reference
I
LQFP48 package
I
2 mA to 20 mA full-scale output current
I
Industrial temperature range of
−40 °C
to +85
°C
Dual 12-bit resolution
125 Msps update rate
Single 3.3 V supply
Dual-port or Interleaved data modes
I
I
I
I
3. Applications
I
Quadrature modulation
I
Medical/test instrumentation
I
Direct IF applications
I
Direct digital frequency synthesis
I
Arbitrary waveform generator
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
4. Ordering information
Table 1.
Ordering information
Package
Name
DAC1201D125HL
LQFP48
Description
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
Version
SOT313-2
Type number
5. Block diagram
DA11 to DA0
WRTA/IQWRT
CLKA/IQCLK
12
INPUT A
LATCH
12
DAC A
LATCH
12
DAC
A
IOUTAP
IOUTAN
REFIO
REFERENCE
AVIRES
BVIRES
GAINCTRL
PWD
DAC1201D125
CLKB/IQRESET
WRTB/IQSEL
DB11 to DB0
12
CONTROL
AMPLIFIER
INPUT B
LATCH
12
DAC B
LATCH
12
DAC
B
IOUTBP
IOUTBN
V
DDA
AGND
V
DDD
DGND
001aai976
Fig 1.
Block diagram
DAC1201D125_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
2 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
6. Pinning information
6.1 Pinning
42 GAINCTRL
40 IOUTBN
45 IOUTAN
47 V
DDA
46 IOUTAP
39 IOUTBP
44 AVIRES
41 BVIRES
43 REFIO
48 MODE
38 AGND
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
1
2
3
4
5
6
7
8
9
37 PWD
36 n.c.
35 n.c.
34 DB0
33 DB1
32 DB2
31 DB3
30 DB4
29 DB5
28 DB6
27 DB7
26 DB8
25 DB9
DB10 24
001aai975
DAC1201D125HL
DA2 10
DA1 11
DA0 12
n.c. 13
n.c. 14
DGND 15
V
DDD
16
WRTA/IQWRT 17
CLKA/IQCLK 18
CLKB/IQRESET 19
WRTB/IQSEL 20
DGND 21
V
DDD
22
DB11 23
Fig 2.
Pin configuration SOT313-2 (LQFP48)
6.2 Pin description
Table 2.
Symbol
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
n.c.
DAC1201D125_1
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
[1]
I
I
I
I
I
I
I
I
I
I
I
I
Description
DAC A, data input bit 11 (MSB)
DAC A, data input bit 10
DAC A, data input bit 9
DAC A, data input bit 8
DAC A, data input bit 7
DAC A, data input bit 6
DAC A, data input bit 5
DAC A, data input bit 4
DAC A, data input bit 3
DAC A, data input bit 2
DAC A, data input bit 1
DAC A, data input bit 0 (LSB)
not connected
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
3 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Pin description
…continued
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
S
O
O
I
I
I/O
I
O
O
S
I
G
S
I
I
I
I
G
S
I
I
I
I
I
I
I
I
I
I
I
I
Type
[1]
Description
not connected
digital ground
digital supply voltage
input write port A/input write IQ in Interleaved mode
input clock port A/input clock IQ in Interleaved mode
input clock port B/reset IQ in Interleaved mode
input write port B/select IQ in Interleaved mode
digital ground
digital supply voltage
DAC B, data input bit 11 (MSB)
DAC B, data input bit 10
DAC B, data input bit 9
DAC B, data input bit 8
DAC B, data input bit 7
DAC B, data input bit 6
DAC B, data input bit 5
DAC B, data input bit 4
DAC B, data input bit 3
DAC B, data input bit 2
DAC B, data input bit 1
DAC B, data input bit 0 (LSB)
not connected
not connected
Power-down mode enable input
analog ground
DAC B current output
complementary DAC B current output
adjust DAC B for full-scale output current
gain control mode enable input
reference voltage input/output
adjust DAC A for full-scale output current
complementary DAC A current output
DAC A current output
analog supply voltage
select between Dual-port or Interleaved mode
Table 2.
Symbol
n.c.
DGND
V
DDD
WRTA/IQWRT
CLKA/IQCLK
CLKB/IQRESET
WRTB/IQSEL
DGND
V
DDD
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
n.c.
n.c.
PWD
AGND
IOUTBP
IOUTBN
BVIRES
GAINCTRL
REFIO
AVIRES
IOUTAN
IOUTAP
V
DDA
MODE
[1]
Type description: S = Supply; G = Ground; I = Input; O = Output; I/O = Input/Output.
DAC1201D125_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
4 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DDD
V
DDA
∆V
DD
V
I
Parameter
digital supply voltage
analog supply voltage
supply voltage difference
input voltage
between analog and digital supply voltage
digital inputs referenced to DGND
pins REFIO, AVIRES, BVIRES
referenced to AGND
V
O
T
stg
T
amb
T
j
[1]
Conditions
[1]
[1]
Min
−0.3
−0.3
−150
−0.3
−0.3
−0.3
−55
−40
-
Max
+5.0
+5.0
+150
+5.5
+5.5
Unit
V
V
mV
V
V
output voltage
storage temperature
ambient temperature
junction temperature
All supplies are connected together.
pins IOUTAP, IOUTAN, IOUTBP and IOUTBN
referenced to AGND
V
DDA
+ 0.3 V
+150
+85
125
°C
°C
°C
8. Thermal characteristics
Table 4.
Symbol
R
th(j-a)
R
th(c-a)
Thermal characteristics
Parameter
thermal resistance from junction to ambient
thermal resistance from case to ambient
Conditions
in free air
in free air
Typ
89.3
60.6
Unit
K/W
K/W
9. Characteristics
Table 5.
Characteristics
V
DDD
= V
DDA
= 3.3 V; AGND and DGND connected together; I
O(fs)
= 20 mA and T
amb
=
−
40
°
C to +85
°
C; typical values
measured at T
amb
= 25
°
C.
Symbol
Supplies
V
DDD
V
DDA
I
DDD
I
DDA
P
tot
P
pd
digital supply voltage
analog supply voltage
digital supply current
analog supply current
total power dissipation
power dissipation in
power-down mode
f
s
= 65 Msps, f
o
= 1 MHz,
V
DD
= 3.0 V to 3.6 V
f
s
= 65 Msps, f
o
= 1 MHz,
V
DD
= 3.0 V to 3.6 V
f
s
= 65 Msps, f
o
= 1 MHz,
V
DD
= 3.0 V to 3.6 V
3.0
3.0
-
-
-
-
3.3
3.3
6
50
185
16.5
3.65
3.65
7
65
260
-
V
V
mA
mA
mW
mW
Parameter
Conditions
Min
Typ
Max
Unit
DAC1201D125_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
5 of 26
京公网安备 11010802033920号
EEWORLD
