ADC1412D series
Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 03 — 6 August 2010
Preliminary data sheet
1. General description
The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1412D is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary
Metal Oxide Semiconductor (CMOS) mode because of a separate digital output supply. It
supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output
standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily
configure the ADC. The device also includes an SPI programmable full-scale to allow a
flexible input voltage range of 1 V to 2 V (peak-to-peak). With excellent dynamic
performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D
is ideal for use in communications, imaging and medical applications.
2. Features and benefits
SNR, 72 dBFS
SFDR, 86 dBc
Sample rate up to 125 Msps
Clock input divider by 2 for less jitter
contribution
Single 3 V supply
Flexible input voltage range:
1 V to 2 V (p-p)
CMOS or LVDS DDR digital outputs
Pin and software compatible with
ADC1212D series
HVQFN64 package
Input bandwidth, 600 MHz
Power dissipation, 855 mW at 80 Msps
Serial Peripheral Interface (SPI)
Duty cycle stabilizer
Fast OuT-of-Range (OTR) detection
INL
±
1 LSB, DNL
±
0.5 LSB
Offset binary, two’s complement, gray
code
Power-down and Sleep modes
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
Software defined radio
NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
4. Ordering information
Table 1.
Ordering information
f
s
(Msps) Package
Name
ADC1412D125HN/C1 125
ADC1412D105HN/C1 105
ADC1412D080HN/C1 80
ADC1412D065HN/C1 65
Description
Version
SOT804-3
SOT804-3
SOT804-3
SOT804-3
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9
×
9
×
0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9
×
9
×
0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9
×
9
×
0.85 mm
HVQFN64 plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9
×
9
×
0.85 mm
Type number
5. Block diagram
SDIO/ODS
SCLK/DFS
CS
ADC1412D
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI INTERFACE
OTRA
INAP
T/H
INPUT
STAGE
INAM
ADC CORE
14-BIT
PIPELINED
OUTPUT
DRIVERS
CMOS:
DA13 to DA0
or
LVDS/DDR:
DA12_DA13_P to DA0_DA1_P,
DA12_DA13_M to DA0_DA1_M
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
CMOS:
DB13 to DB0
or
LVDS/DDR:
DB12_DB13_P to DB0_DB1_P
DB12_DB13_M to DB0_DB1_M
OTRB
CLKP
CLKM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
OUTPUT
DRIVERS
INBP
T/H
INPUT
STAGE
INBM
ADC CORE
14-BIT
PIPELINED
OUTPUT
DRIVERS
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
CTRL
REFBT
REFBB
VCMB
VCMA
SENSE VREF
REFAB
REFAT
005aaa096
Fig 1. Block diagram
ADC1412D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 03 — 6 August 2010
2 of 40
NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 CMOS outputs selected
6.1.1 Pinning
62 SENSE
50 VDDO
terminal 1
index area
INAP
INAM
AGND
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
1
2
3
4
5
6
7
8
9
49 VDDO
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 DAV
41 n.c.
40 DB0
39 DB1
38 DB2
37 DB3
36 DB4
35 DB5
34 DB6
33 DB7
VDDO 32
005aaa097
64 VDDA
61 VDDA
60 DECA
59 OTRA
63 VREF
58 DA13
57 DA12
56 DA11
55 DA10
54 DA9
53 DA8
DB10 28
52 DA7
DB9 29
ADC1412D
HVQFN64
AGND 10
REFBB 11
REFBT 12
VCMB 13
AGND 14
INBM 15
INBP 16
VDDA 17
VDDA 18
SCLK/DFS 19
SDIO/ODS 20
CS 21
CTRL 22
DECB 23
OTRB 24
DB13 25
DB12 26
DB11 27
DB8 30
VDDO 31
Transparent top view
Fig 2.
Pin configuration with CMOS digital outputs selected
6.1.2 Pin description
Table 2.
Symbol
INAP
INAM
AGND
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
AGND
REFBB
REFBT
ADC1412D_SER
Pin description (CMOS digital outputs)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Type
[1]
I
I
G
O
O
O
G
I
I
G
O
O
Description
analog input; channel A
complementary analog input; channel A
analog ground
common-mode output voltage; channel A
top reference; channel A
bottom reference; channel A
analog ground
clock input
complementary clock input
analog ground
bottom reference; channel B
top reference; channel B
© NXP B.V. 2010. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 03 — 6 August 2010
51 DA6
3 of 40
NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
Pin description (CMOS digital outputs)
…continued
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Type
[1]
O
G
I
I
P
P
I
I/O
I
I
O
O
O
O
O
O
O
O
P
P
O
O
O
O
O
O
O
O
-
O
O
O
O
O
O
O
P
P
O
O
O
O
O
O
Description
common-mode output voltage; channel B
analog ground
complementary analog input; channel B
analog input; channel B
analog power supply
analog power supply
SPI clock/data format select
SPI data IO/output data standard
SPI chip select
control mode select
regulator decoupling node; channel B
out of range; channel B
data output bit 13 (Most Significant Bit (MSB)); channel B
data output bit 12; channel B
data output bit 11; channel B
data output bit 10; channel B
data output bit 9; channel B
data output bit 8; channel B
output power supply
output power supply
data output bit 7; channel B
data output bit 6; channel B
data output bit 5; channel B
data output bit 4; channel B
data output bit 3; channel B
data output bit 2; channel B
data output bit 1; channel B
data output bit 0 (Least Significant Bit (LSB)); channel B
not connected
data valid output clock
data output bit 0 (LSB); channel A
data output bit 1; channel A
data output bit 2; channel A
data output bit 3; channel A
data output bit 4; channel A
data output bit 5; channel A
output power supply
output power supply
data output bit 6; channel A
data output bit 7; channel A
data output bit 8; channel A
data output bit 9; channel A
data output bit 10; channel A
data output bit 11; channel A
© NXP B.V. 2010. All rights reserved.
Table 2.
Symbol
VCMB
AGND
INBM
INBP
VDDA
VDDA
SCLK/DFS
SDIO/ODS
CS
CTRL
DECB
OTRB
DB13
DB12
DB11
DB10
DB9
DB8
VDDO
VDDO
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
n.c.
DAV
DA0
DA1
DA2
DA3
DA4
DA5
VDDO
VDDO
DA6
DA7
DA8
DA9
DA10
DA11
ADC1412D_SER
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 03 — 6 August 2010
4 of 40
NXP Semiconductors
ADC1412D series
CMOS or LVDS DDR digital outputs
Pin description (CMOS digital outputs)
…continued
Pin
57
58
59
60
61
62
63
64
Type
[1]
O
O
O
O
P
I
I/O
P
Description
data output bit 12; channel A
data output bit 13 (MSB); channel A
out-of-range; channel A
regulator decoupling node; channel A
analog power supply
reference programming pin
voltage reference input/output
analog power supply
Table 2.
Symbol
DA12
DA13
OTRA
DECA
VDDA
SENSE
VREF
VDDA
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
6.2 LVDS/DDR outputs selected
6.2.1 Pinning
58 DA12_DA13_M
56 DA10_DA11_M
57 DA12_DA13_P
55 DA10_DA11_P
54 DA8_DA9_M
52 DA6_DA7_M
53 DA8_DA9_P
51 DA6_DA7_P
62 SENSE
50 VDDO
terminal 1
index area
INAP
INAM
AGND
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
1
2
3
4
5
6
7
8
9
49 VDDO
48 DA4_DA5_M
47 DA4_DA5_P
46 DA2_DA3_M
45 DA2_DA3_P
44 DA0_DA1_ M
43 DA0_DA1_P
42 DAVP
41 DAVM
40 DB0_DB1_P
39 DB0_DB1_M
38 DB2_DB3_P
37 DB2_DB3_M
36 DB4_DB5_P
35 DB4_DB5_M
34 DB6_DB7_P
33 DB6_DB7_M
VDDO 32
005aaa098
64 VDDA
61 VDDA
60 DECA
CS 21
59 OTRA
CTRL 22
63 VREF
ADC1412D
HVQFN64
AGND 10
REFBB 11
REFBT 12
VCMB 13
AGND 14
INBM 15
INBP 16
VDDA 17
VDDA 18
SCLK/DFS 19
SDIO/ODS 20
DECB 23
OTRB 24
DB12_DB13_M 25
DB12_DB13_P 26
DB10_DB11_M 27
DB10_DB11_P 28
DB8_DB9_M 29
DB8_DB9_P 30
VDDO 31
Transparent top view
Fig 3.
Pin configuration with LVDS/DDR digital outputs selected
ADC1412D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 03 — 6 August 2010
5 of 40
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