Freescale Semiconductor
Technical Data
Document Number: MC13192
Rev. 3.3, 04/2008
MC13192
MC13192
2.4 GHz Low Power Transceiver
for the IEEE
®
802.15.4 Standard
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Package Information
Plastic Package
Case 1311-03
(QFN-32)
Ordering Information
Device
MC13192FC
MC13192FCR2
(Tape and reel)
Device Marking
13192
13192
Package
QFN-32
QFN-32
1
Introduction
Contents
1
2
3
4
5
6
7
8
9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
Data Transfer Modes . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . 11
Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14
Applications Information . . . . . . . . . . . . . . . 17
Packaging Information . . . . . . . . . . . . . . . . . 23
The MC13192 is a short range, low power, 2.4 GHz
Industrial, Scientific, and Medical (ISM) band
transceivers. The MC13192 contains a complete
802.15.4 physical layer (PHY) modem designed for the
IEEE
®
802.15.4 Standard which supports peer-to-peer,
star, and mesh networking.
The MC13192 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13192 can be
used with Freescale’s IEEE 802.15.4 MAC and
BeeStack, which is Freescale’s ZigBee 2006 compliant
protocol stack.
When combined with an appropriate microcontroller
(MCU), the MC13192 provide a cost-effective solution
for short-range data links and networks. Interface with
the MCU is accomplished using a four wire serial
peripheral interface (SPI) connection and an interrupt
request output which allows for the use of a variety of
processors. The software and processor can be scaled to
fit applications ranging from simple point-to-point
systems, through complete ZigBee™ networking.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007, 2008. All rights reserved.
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Features
For more detailed information about MC13192 operation, refer to the
MC13192 Reference Manual,
(MC13192RM).
Applications include, but are not limited to, the following:
• Remote control and wire replacement in industrial systems such as wireless sensor networks
• Factory automation and motor control
• Energy Management (lighting, HVAC, etc.)
• Asset tracking and monitoring
Potential consumer applications include:
• Home automation and control (lighting, thermostats, etc.)
• Human interface devices (keyboard, mice, etc.)
• Remote control
• Wireless toys
The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), PLL with internal voltage
controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and
decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0
MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request
output are used for receive (RX) and transmit (TX) data transfer and control.
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Features
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Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode
(compatible with the 802.15.4 Standard)
Operates on one of 16 selectable channels in the 2.4 GHz band
RX sensitivity of <-92 dBm (typical) at 1.0% packet error rate
0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power
Recommended power supply range: 2.0 to 3.4 V
Buffered transmit and receive data packets for simplified use with low cost MCUs
Three power down modes for power conservation:
— < 1 µA Off current
— 1 µA Typical Hibernate current
— 35 µA Typical Doze current (no CLKO)
Four internal timer comparators available to supplement MCU resource
Programmable frequency clock output (CLKO) for use by MCU
Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external
variable capacitors and allows for automated production frequency calibration.
Seven general purpose input/output (GPIO) signals
Operating temperature range: -40 °C to 85 °C
Small form factor QFN-32 Package
MC13192 Technical Data, Rev. 3.3
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Freescale Semiconductor
Features
—
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—
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RoHS compliant
Meets moisture sensitivity level (MSL) 3
260 °C peak reflow temperature
Meets lead-free requirements
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Software Features
Simple MAC (SMAC)
802.15.4 Standard-Compliant MAC
ZigBee-Compliant Network Stack
2.1
Freescale provides a wide range of software functionality to complement the MC13192 hardware. There
are three levels of application solutions:
1. Simple proprietary wireless connectivity.
2. User networks built on the 802.15.4 MAC standard.
3. ZigBee-compliant network stack.
2.1.1
•
•
•
•
Small memory footprint (about 3 Kbytes typical)
Supports point-to-point and star network configurations
Proprietary networks
Source code and application examples provided
2.1.2
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•
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Supports star, mesh and cluster tree topologies
Supports beaconed networks
Supports GTS for low latency
Multiple power saving modes (idle doze, hibernate)
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Supports ZigBee 1.0 specification
Supports star, mesh and tree networks
Advanced Encryption Standard (AES) 128-bit security
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MC13192 Technical Data, Rev. 3.3
Freescale Semiconductor
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Block Diagrams
3
Block Diagrams
Figure 1
shows a simplified block diagram of the MC13192 which is an 802.15.4 Standard compatible
transceiver that provides the functions required in the physical layer (PHY) specification.
V DDLO 2
Figure 2
shows the basic system block diagram for the MC13192 in an application. Interface with the
transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control
(MAC), drivers, and network and application software (as required) reside on the host processor. The host
can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application
requirements.
Digital Transceiver
RAM Arbiter
IRQ Arbiter
Timer
Frequency
Generation
RAM
CPU
Analog
Transmitter
Application
Network
Voltage
Regulators
Power Up
Management
Buffer RAM
MAC
PHY Driver
Figure 2. System Level Block Diagram
MC13192 Technical Data, Rev. 3.3
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Freescale Semiconductor
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R F IN +
R F IN -
Correlator
LN A
1 s t IF M ix er
IF = 6 5 M Hz
2nd IF M ix er
IF = 1 M Hz P M A
Dec im ation
F ilter
B as e band
M ix e r
M atc hed
F ilter
CCA
DC D
R ec eiv e
P ac k e t R A M
AGC
256 M Hz
A nalog
R egulator
P ow er-U p
C ontrol
Lo gic
Digital
R egulator L
Digital
R e gulato r H
C ry s tal
R egulator
R ec e iv e R A M
A rbiter
VC O
R egulator
V DDA
VBAT T
V DDIN T
Synch & Det
Symbol
P ac k et
P roc e s s or
V DDD
V DDV C O
÷
4
P ro gram m able
P res c aler
24 B it E v ent T im er
S equ enc e
M ana ger
(C o ntrol L ogic )
R XT XEN
SERIAL
PERIPHERAL
INTERFACE
(SPI)
4 P ro gram m able
T im er C o m parators
CE
M OSI
M IS O
S P IC L K
ATT N
R ST
X T A L1
X T A L2
C ry s ta l
O s c illa tor
16 M Hz
S y n th e size r
T rans m it
P ac k et R A M 2
T rans m it
P ac k et R A M 1
G P IO 1
G P IO 2
G P IO 3
G P IO 4
G P IO 5
G P IO 6
G P IO 7
S y m bol
G ene ra tion
IR Q
A rbiter
IR Q
V DDLO 1
2. 45 G Hz
V CO
T rans m it R A M
A rbite r
PAO+
PAO-
PA
P has e S h ift M o dulato r
MUX
C LK O
FCS
G e neratio n
Heade r
G ene ra tion
Figure 1. MC13192 Simplified Block Diagram
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Analog Receiver
Control
Logic
Microcontroller
SPI
ROM
(Flash)
SPI
and GPIO
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Data Transfer Modes
4
Data Transfer Modes
The MC13192 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
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Packet Structure
4 bytes
1 byte
SFD
1 byte
FLI
Preamble
4.1
Figure 3
shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The
MC13192 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame
Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
125 bytes maximum
Payload Data
2 bytes
FCS
Figure 3. MC13192 Packet Structure
4.2
Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13192 is in packet mode, the data is processed as an entire packet. The MCU is notified that an
entire packet has been received via an interrupt.
If the MC13192 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis.
Figure 4
shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above 802.15.4 Standard requirements.
MC13192 Technical Data, Rev. 3.3
Freescale Semiconductor
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