Si5010-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5010 clock and data recovery (CDR) device by
providing access to all of the Si5010 I/Os. Device
performance can be evaluated by following the Test
Configuration section below. Specific performance
metrics include jitter tolerance, jitter generation, and
jitter transfer.
Power Supply
The evaluation board requires one 2.5 V supply. Supply
filtering is placed on the board to filter typical system
noise components, however, initial performance testing
should use a linear supply capable of supplying 2.5 V
±5% dc.
CAUTION:
The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 2.5 V relative to chassis
GND.
Self-Calibration
The Si5010 device provides an internal self-calibration
function that optimizes the loop gain parameters within
the internal DSPLL
TM
. Self-calibration is initiated by a
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
On the Si5010-EVB board, a voltage detector IC is
utilized to initiate self-calibration. The voltage detector
drives the PWRDN/CAL signal low after the supply
voltage has reached a specific voltage level. This circuit
is described in Silicon Laboratories application note
AN42. On the Si5010-EVB, the PWRDN/CAL signal is
also accessible via a jumper located in the lower left-
hand corner of the evaluation board. PWRDN/CAL is
wired to the signal post adjacent to the 2.5 V post.
Device Powerdown
The CDR can be powered down via the PWRDN/CAL
signal. When asserted the evaluation board will draw
minimal current. PWRDN/CAL is controlled via one
jumper located in the lower left-hand corner of the
evaluation board. PWRDN/CAL is wired to the signal
post adjacent to the 2.5 V post.
CLKOUT, DATAOUT, DATAIN
These high-speed I/Os are wired to the board perimeter
on 30 mil (0.030 inch) 50
Ω
microstrip lines to the end-
launch SMA jacks as labeled on the PCB. These I/Os
are ac coupled to simplify direct connection to a wide
array of standard test hardware. Because each of these
signals are differential both the positive (+) and negative
(–) terminals must be terminated to 50
Ω.
Terminating
only one side will adversely degrade the performance of
the CDR. The inputs are terminated on the die with 50
Ω
resistors.
2
622 M bps
To improve the DATAOUT eye-diagram, short 100
Ω
transmission line segments precede the 50
Ω
high-
speed traces. These segments increase the interface
bandwidth from the chip to the 50
Ω
traces and reduce
data inter-symbol-interference. Please refer to Silicon
Laboratories application note AN43 for more details.
Note:
The 50
Ω
termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50
Ω
+ 50
Ω
= 100
Ω.
REFCLK
REFCLK is used to center the frequency of the
DSPLL™ so that the device can lock to the data. Ideally
the REFCLK frequency should be 19.44 77.76, or
155.52 MHz, and must have a frequency accuracy of
±100 PPM.
Internally,
the
CDR
automatically
recognizes the REFCLK frequency within one of these
three frequency ranges. REFCLK is ac coupled to the
SMA jacks located on the top side of the evaluation
board.
RATESEL
RATESEL is used to configure the CDR to recover clock
and data at different data rates. RATESEL is a binary
input that is controlled via a jumper located in the lower
left-hand corner of the evaluation board. RATESEL is
wired to the center post (signal post) between 2.5 V and
GND. For example, the OC-12 data rate is selected by
jumping RATESEL to 0.0 V.
The table given on the evaluation board lists
approximate data rates for the jumper configurations
shown in Figure 1.
2.5 V
GND
2.5 V
RATESEL
PW RDN/
CAL
RATESEL
PW RDN/
CAL
Figure 1. RATESEL Jumper Configurations
Loss-of-Lock (LOL)
LOL is an indicator of the relative frequency between
the data and the REFCLK. LOL will assert when the
frequency difference is greater than ±600 PPM. In order
to prevent LOL from de-asserting prematurely, there is
hysterisis in returning from the out-of-lock condition.
LOL will be de-asserted when the frequency difference
is less than ±300 PPM.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Rev. 1.0
GND
155 M bps
Si5010-EVB
Test Configuration
The three critical tests that are typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
generation. By connecting the Si5010 Evaluation Board
as shown in Figure 2, all three measurements can be
easily made.
REFCLK should be within ±100 PPM of 19.44, 77.76, or
155.52 MHz. RATESEL must be configured to match
the desired data rate, and PWRDN/CAL must be
unjumpered.
Jitter Tolerance:
Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a modulation source, a jitter
analyzer, a pattern analyzer, and a pulse generator (all
unconnected high-speed outputs must be terminated to
50
Ω).
During this test the Jitter Analyzer causes a
modulation on the data pattern which drives the DATAIN
ports of the CDR. The Bit-Error-Rate (BER) is monitored
on the Pattern Analyzer. The modulation (jitter)
frequency and amplitude is recorded when the BER
approaches a specified threshold.
Jitter Generation:
Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test, there is no
modulation of the Data Clock, so the data that is sent to
the CDR is jitter free. The Jitter Analyzer measures the
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer:
Referring to Figure 2, this test requires
a pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
Rev. 1.0
3
Power technology
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