R1LP0408C-I Series
Wide Temperature Range Version
4 M SRAM (512-kword
×
8-bit)
REJ03C0067-0100Z
Rev. 1.00
Aug.01.2003
Description
The R1LP0408C-I is a 4-Mbit static RAM organized 512-kword
×
8-bit. R1LP0408C-I Series has realized
higher density, higher performance and low power consumption by employing CMOS process technology
(6-transistor memory cell). The R1LP0408C-I Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin TSOP II.
Features
•
Single 5 V supply: 5 V
±
10%
•
Access time: 55/70 ns (max)
•
Power dissipation:
Active: 10 mW/MHz (typ)
Standby: 4
µW
(typ)
•
Completely static memory.
No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output.
Three state output
•
Directly TTL compatible.
All inputs and outputs
•
Battery backup operation.
•
Operating temperature:
−40
to +85°C
Rev.1.00, Aug.01.2003, page 1 of 13
R1LP0408C-I Series
Ordering Information
Type No.
R1LP0408CSP-5SI
R1LP0408CSP-7LI
R1LP0408CSB-5SI
R1LP0408CSB-7LI
R1LP0408CSC-5SI
R1LP0408CSC-7LI
Access time
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
400-mil 32-pin plastic TSOP II reverse (32P3Y-J)
400-mil 32-pin plastic TSOP II (32P3Y-H)
Package
525-mil 32-pin plastic SOP (32P2M-A)
Rev.1.00, Aug.01.2003, page 2 of 13
R1LP0408C-I Series
Pin Arrangement
32-pin SOP
32-pin TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
CC
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
32-pin TSOP (reverse)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS# (CS)
OE# (OE)
WE# (WE)
V
CC
V
SS
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
Rev.1.00, Aug.01.2003, page 3 of 13
R1LP0408C-I Series
Block Diagram
LSB
V
CC
V
SS
•
•
•
•
•
MSB
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
Row
Decoder
Memory Matrix
2,048
×
2,048
I/O0
Input
Data
Control
I/O7
•
•
Column I/O
Column Decoder
•
•
LSB A3 A2A1A0 A4 A5 A6 A7 MSB
•
•
CS#
WE#
OE#
Timing Pulse Generator
Read/Write Control
Rev.1.00, Aug.01.2003, page 4 of 13
R1LP0408C-I Series
Operation Table
WE#
×
H
H
L
L
CS#
H
L
L
L
L
OE#
×
H
L
H
L
Mode
Not selected
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
I/O0 to I/O7
High-Z
High-Z
Dout
Din
Din
Ref. cycle
Read cycle
Write cycle (1)
Write cycle (2)
Note: H: V
IH
, L: V
IL
,
×:
V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Terminal voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature range
Storage temperature range under bias
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
−0.5
to +7.0
−0.5*
to V
CC
+ 0.3*
1
2
Unit
V
V
W
°C
°C
°C
0.7
−40
to +85
−65
to +150
−40
to +85
Notes: 1. V
T
min:
−3.0
V for pulse half-width
≤
30 ns.
2. Maximum voltage is +7.0 V.
DC Operating Conditions
(Ta =
−40
to +85°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Note:
V
IH
V
IL
Min
4.5
0
2.2
−0.3*
1
Typ
5.0
0
Max
5.5
0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
1. V
IL
min:
−3.0
V for pulse half-width
≤
30 ns.
Rev.1.00, Aug.01.2003, page 5 of 13