SN74AHC74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS489 – JUNE 2003
D
D
D
D
D
D
D
D
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
†
EPIC (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
–55°C to 125°C
55°C
SOIC – D
PACKAGE‡
Tape and reel
ORDERABLE
PART NUMBER
SN74AHC74MDREP
TOP-SIDE
MARKING
AHC74MEP
TSSOP – PW
Tape and reel
SN74AHC74MPWREP
AHC74EP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SN74AHC74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS489 – JUNE 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
OUTPUTS
Q
H
L
H†
H
L
Q0
Q
L
H
H†
L
H
Q0
† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol
‡
1PRE
1CLK
1D
1CLR
2PRE
2CLK
2D
2CLR
4
3
2
1
10
11
12
8
13
2Q
S
C1
1D
R
9
6
1Q
5
1Q
2Q
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
Q
TG
C
C
C
D
TG
TG
TG
C
C
Q
C
CLR
C
C
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74AHC74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS489 – JUNE 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
High-level output current
VCC = 2 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 2 V
IOL
Low-level output current
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 3 V
VCC = 5.5 V
0
0
2
1.5
2.1
3.85
0.5
0.9
1.65
5.5
VCC
–50
–4
–8
50
4
8
100
20
V
V
V
V
MAX
5.5
UNIT
V
m
A
mA
m
A
mA
ns/V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–55
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN74AHC74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS489 – JUNE 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = –50
m
A
VOH
IOH = –4 mA
IOH = –8 mA
IOL = 50
m
A
VOL
IOL = 4 mA
IOL = 8 mA
II
ICC
Ci
VI = 5.5 V or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
3V
4.5 V
3V
4.5 V
2V
3V
4.5 V
3V
4.5 V
0 V to 5.5 V
5.5 V
5V
2
TA = 25°C
MIN
TYP
MAX
1.9
2.9
4.4
2.58
3.94
0.1
0.1
0.1
0.36
0.36
±0.1
2
10
2
3
4.5
MIN
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.5
0.5
±1
20
V
V
MAX
UNIT
m
A
m
A
pF
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
th
Pulse duration
PRE or CLR low
CLK
Data
Setup time before CLK↑
Hold time, data after CLK↑
PRE or CLR inactive
6
6
6
5
0.5
MIN
7
7
7
5
0.5
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
th
Pulse duration
PRE or CLR low
CLK
Data
Setup time before CLK↑
Hold time, data after CLK↑
PRE or CLR inactive
5
5
5
3
0.5
MIN
5
5
5
3
0.5
MAX
UNIT
ns
ns
ns
4
POST OFFICE BOX 655303
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SN74AHC74-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCLS489 – JUNE 2003
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
Q or Q
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
80
50
125
75
7.6
7.6
6.7
6.7
10.1
10.1
9.2
9.2
12.3
12.3
11.9
11.9
15.8
15.8
15.4
15.4
MIN
70
45
1
1
1
1
1
1
1
1
14.5
14.5
14
14
18
18
17.5
17.5
MAX
UNIT
MHz
ns
ns
ns
ns
PRE or CLR
CLK
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
Q or Q
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
130
90
170
115
4.8
4.8
4.6
4.6
6.3
6.3
6.1
6.1
7.7
7.7
7.3
7.3
9.7
9.7
9.3
9.3
MIN
110
75
1
1
1
1
1
1
1
1
9
9
8.5
8.5
11
11
10.5
10.5
MAX
UNIT
MHz
ns
ns
ns
ns
PRE or CLR
CLK
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25°C (see Note 4
)
PARAMETER
VOL(P)
VOL(V)
VOH(V)
VIH(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
4.7
3.5
1.5
MIN
MAX
0.8
–0.8
UNIT
V
V
V
V
V
VIL(D)
Low-level dynamic input voltage
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
32
UNIT
pF
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•
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5
51mcu
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