CAT28C16APA-20 datasheet, PDF - EEWORLD Datasheet

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CAT28C16APA-20: DescriptionEEPROM, 2KX8, 200ns, Parallel, CMOS, PDIP24, PLASTIC, DIP-24; Categorystorage storage; File Size413KB，10 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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CAT28C16APA-20 Overview

EEPROM, 2KX8, 200ns, Parallel, CMOS, PDIP24, PLASTIC, DIP-24

CAT28C16APA-20 Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	DIP,
Reach Compliance Code	unknown
Is Samacsys	N
Maximum access time	200 ns
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	31.875 mm
memory density	16384 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	24
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	2KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Programming voltage	5 V
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Maximum write cycle time (tWC)	10 ms
Base Number Matches	1

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CAT28C16A

16K-Bit CMOS PARALLEL EEPROM

FEATURES

Fast read access times: 90 ns, 120 ns, 200 ns

Low power CMOS cissipation:

GEN

ALO

End of write detection:

DATA

polling

Hardware write protection

CMOS and TTL compatible I/O

10,000 or 100,000 Program/erase cycles

10 or 100 year data retention

Commercial, industrial and automotive

–Active: 25 mA Max.

–Standby: 100

A Max.

Simple write operation:

–On-chip address and data latches

–Self-timed write cycle with auto-clear

Fast write cycle time: 10ms max

temperature ranges

DESCRIPTION

The CAT28C16A is a fast, low power, 5V-only CMOS

Parallel EEPROM organized as 2K x 8-bits. It requires a

simple interface for in-system programming. On-chip

address and data latches, self-timed write cycle with

auto-clear and V

power up/down write protection

eliminate additional timing and protection hardware.

DATA

Polling signals the start and end of the self-timed

write cycle. Additionally, the CAT28C16A features hard-

ware write protection.

The CAT28C16A is manufactured using Catalyst’s ad-

vanced CMOS floating gate technology. It is designed to

endure 10,000 program/erase cycles and has a data

retention of 10 years. The device is available in JEDEC

approved 24-pin DIP and SOIC or 32-pin PLCC pack-

ages.

BLOCK DIAGRAM

A4–A10

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

ROW

DECODER

2,048 x 8

EEPROM

ARRAY

VCC

HIGH VOLTAGE

GENERATOR

CONTROL

LOGIC

I/O BUFFERS

TIMER

DATA POLLING

I/O0–I/O7

A0–A3

ADDR. BUFFER

& LATCHES

COLUMN

DECODER

Characteristics subject to change without notice

Doc. No. 1076, Rev. D

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