IS61WV51216EDALL
IS61/64WV51216EDBLL
512K x 16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
FEATURES
• High-speed access times: 8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
•
Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single Power Supply
– V
dd
= 1.65V to 2.2V (IS61WV51216EDALL)
– V
dd
= 2.4V to 3.6V (IS61/64WV51216EDBLL)
• Packages available:
–
48-ball miniBGA (6mm x 8mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
FEBRUARY 2013
DESCRIPTION
The
ISSI
IS61WV51216EDALL and
IS61/64WV51216EDBLL are high-speed, 8M-bit static
RAMs organized as 512K words by 16 bits. It is fabri-
cated using
ISSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and
low power consumption devices.
When
CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip En-
able and Output Enable inputs, CE
and
OE. The active
LOW Write Enable (WE)
controls both writing and read-
ing of the memory. A data byte allows Upper Byte (UB)
and Lower Byte (LB)
access.
The device is packaged in the JEDEC standard 44-pin
TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A18
Decoder
Memory
Lower IO
Array-
512Kx8
8
4
ECC
Array-
512K
x4
Memory
Upper IO
Array-
512Kx8
8
4
ECC
Array-
512K
x4
IO0-7
IO8-15
8
8
I/O Data
Circuit
8
ECC
8
ECC
12
12
Column I/O
/CE
/OE
/WE
/UB
/LB
Control
Circuit
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/20/2013
1
IS61WV51216EDALL
IS61/64WV51216EDBLL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
d
Out
High-Z
d
Out
d
in
High-Z
d
in
High-Z
High-Z
High-Z
High-Z
d
Out
d
Out
High-Z
d
in
d
in
V
DD
Current
i
sb
1
, i
sb
2
i
CC
i
CC
i
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
V
dd
t
stg
P
t
Parameter
Terminal Voltage with Respect to GND
V
dd
Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
dd
+ 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
in
C
i/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
in
= 0V
V
Out
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a
= 25°C,
f = 1 MHz, V
dd
= 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/20/2013
Special Edition for Assessment Centres
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