PRA182C2328K0.5%0.02%R0031 datasheet, PDF

Datasheet> All Categories > Passive components> The resistor> PRA182C2328K0.5%0.02%R0031

PRA182C2328K0.5%0.02%R0031: DescriptionArray/Network Resistor, Bussed, Thin Film, 0.2W, 328000ohm, 150V, 0.5% +/-Tol, -10,10ppm/Cel, 1412,; CategoryPassive components The resistor; File Size80KB，5 Pages; ManufacturerVishay; Websitehttp://www.vishay.com

Download Datasheet Parametric View All

PRA182C2328K0.5%0.02%R0031 Overview

Array/Network Resistor, Bussed, Thin Film, 0.2W, 328000ohm, 150V, 0.5% +/-Tol, -10,10ppm/Cel, 1412,

PRA182C2328K0.5%0.02%R0031 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	983568771
package instruction	SMT, 1412
Reach Compliance Code	compliant
ECCN code	EAR99
structure	Chip
Network Type	Bussed
Number of terminals	4
Maximum operating temperature	155 °C
Minimum operating temperature	-55 °C
Package height	0.4 mm
Package length	3.64 mm
Package form	SMT
Package width	3 mm
method of packing	Box
Rated power dissipation(P)	0.2 W
resistance	328000 Ω
Resistor type	ARRAY/NETWORK RESISTOR
series	PRA (CNW)
size code	1412
technology	THIN FILM
Temperature Coefficient	10 ppm/°C
Tolerance	0.5%
Operating Voltage	150 V

Preview

Download Datasheet

View All

PRA 100, 135, 182 (CNW)

Vishay Sfernice

High Precision Resistor Chip Arrays

FEATURES

•

High stability passivated nichrome resistive

layer 0.02 % on ratio, 1000 h at Pn at + 70 °C

•

Tight TCR (10 ppm/°C) and TCR tracking

(to 1 ppm/°C)

•

Very low noise < 35 dB and voltage coefficient

< 0.01 ppm/V

•

Ratio tolerance to 0.01 % (R

≥

200R)

•

Pre-tinned terminations over nickel barrier

•

High temperature option (200 °C)

•

SMD wraparound chip resistor array

•

Compliant to RoHS directive 2002/95/EC

PRA arrays can be used in most applications requiring a

matched pair (or set) of resistor elements. The networks

provide 1 ppm/°C TCR tracking, a ratio tolerance as tight as

0.01 % and outstanding stability. They are available in 1 mm,

1.35 mm and 1.82 mm pitch.

TYPICAL PERFORMANCE

ABS

TCR

TOL

10 ppm/°C

ABS

0.1 %

TRACKING

2 ppm/°C

RATIO

0.05 %

DIMENSIONS

Suggested Land Pattern

I: Independent resistors

Termination

Electrical diagram

DIM.

(1)

PRA 100

1.6

0.4

0.65

+ 0.2

- 0.1

+ 0.2

- 0.2

+ 0.15

- 0.15

PRA 135

mil

1.85

0.4

1.05

+ 0.2

- 0.1

+ 0.2

- 0.2

+ 0.15

- 0.15

PRA 182

mil

3.0

0.4

1.3

+ 0.2

- 0.1

+ 0.2

- 0.2

+ 0.35

- 0.15

mil

118

Number

of resistors:

2 to

R1 = R2 = ... R8

25.5

0.25

E = (N x F) ± 0.2 mm

0.4

+ 0.1

-0

E = (N x F) ± 8 mil

53.1

41.3

31.5

1.82

0.4

+ 0.1

-0

C: One common point

resistors

27.5

23.5

1.35

0.4

+ 0.1

-0

59.8

70.8

0.7

0.3

0.6

1.05

0.3

0.8

1.52

0.3

1.8

Note

(1)

E depends on number of resistors

* Pb containing terminations are not RoHS compliant, exemptions may apply

** Please see document “Vishay Material Category Policy”:

www.vishay.com/doc?99902

www.vishay.com

For technical questions, contact:

sfer@vishay.com

Number

of resistors:

2 to

R1 = R2 = ... R8

Document Number: 53033

Revision: 17-Aug-09

Recommended Resources

Internal functional block diagram of HIP6302 chip

Apply LOGO! Lighting control circuit to realize multi-function switchb

Rectifier circuit

Leakage pulse detector circuit diagram A

Instrumental moisture alarm

12V, 18V dual-channel regulated power supply circuit

[RVB2601 Creative Application Development] 3. RGB three-color breathing light of RVB2601: [i=s]This post was last edited by kit7828 on 2022-3-10 14:00[/i]There is a ch2601_rgb_marquee_demo in the routine of Pingtou Ge, which is a demo to realize the three-color marquee effect of RGB LED la...; kit7828 XuanTie RISC-V Activity Zone

C6000 DSP Architecture: The high-performance C6000 DSP architecture has 8 parallel functional units, 2 groups of registers, separate program and data storage; 256-bit instruction fetch package, which can fetch 8 32-bit instr...; Jacktang Microcontroller MCU

Several classic FPGA verification books: SystemVerilog is a hardware description and verification language (HDVL). It is based on the IEEE1364-2001 Verilog hardware description language (HDL) and has been extended to include C language data ...; arui1999 Download Centre

FPGA learning experience - matrix keyboard: ...; 至芯科技FPGA大牛 FPGA/CPLD

Welcome the moderator "天意无罪" to take office~~: I'm glad that another netizen has joined the EEWorld moderator team~Here is the new moderator information: Username: God is innocent Responsible section: Comprehensive technical exchange Personal intr...; okhxyyo Integrated technical exchanges

Task stack overflow detection mechanism in FreeRTOS: In FreeRTOS, each task has its own stack, the size of which is determined by the function parameters of the xTaskCreate function when the task is created.However, when the stack space used by a task e...; MamoYU Real-time operating system RTOS

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components