AT94S05AL-25BQI datasheet, PDF

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AT94S05AL-25BQI: DescriptionSecure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM; File Size426KB，32 Pages; ManufacturerAtmel (Microchip)

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AT94S05AL-25BQI Overview

Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM

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Features

•

Multichip Module Containing Field Programmable System Level Integrated Circuit

•

(FPSLIC

) and Secure Configuration EEPROM Memory

512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

Programming (ISP)

Field Programmable System Level Integrated Circuit (FPSLIC)

– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR

Core and

Extensive Data and Instruction SRAM

5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

™

– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM

– High-performance DSP Optimized FPGA Core Cell

– Dynamically Reconfigurable In-System – FPGA Configuration Access Available

On-chip from AVR Microcontroller Core to Support Cache Logic

Designs

– Very Low Static and Dynamic Power Consumption – Ideal for Portable and

Handheld Applications

Patented AVR Enhanced RISC Architecture

– 120+ Powerful Instructions – Most Single Clock Cycle Execution

– High-performance Hardware Multiplier for DSP-based Systems

– Approaching 1 MIPS per MHz Performance

– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers

– Low-power Idle, Power-save, and Power-down Modes

– 100 µA Standby and Typical 2-3 mA per MHz Active

Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM

– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM

– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM

JTAG (IEEE Std. 1149.1 Compliant) Interface

– Extensive On-chip Debug Support

– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)

AVR Fixed Peripherals

– Industry-standard 2-wire Serial Interface

– Two Programmable Serial UARTs

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture

Modes and Dual 8-, 9- or 10-bit PWM

Support for FPGA Custom Peripherals

– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly

Accessible to FPGA

– FPGA Macro Library of Custom Peripherals

Up to 16 FPGA Supplied Internal Interrupts to AVR

Up to Four External Interrupts to AVR

8 Global FPGA Clocks

– Two FPGA Clocks Driven from AVR Logic

– FPGA Global Clock Access Available from FPGA Core

Multiple Oscillator Circuits

– Programmable Watchdog Timer with On-chip Oscillator

– Oscillator to AVR Internal Clock Circuit

– Software-selectable Clock Frequency

– Oscillator to Timer/Counter for Real-time Clock

•

Secure

5K - 40K Gates

of AT40K FPGA

with 8-bit

Microcontroller,

up to 36 Kbytes

of SRAM and

On-chip

Program

Storage

EEPROM

AT94S

Secure Series

Programmable

SLI

•

2314E–FPSLI–6/05

2. Internal Architecture

For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K FPSLIC

datasheet and the AT17 Series Configuration Memory datasheet, available on the Atmel web

site at http://www.atmel.com. This document only describes the differences between the AT94S

Secure FPSLIC and the AT94K FPSLIC.

3. FPSLIC and Configurator Interface

• Fully In-System Programmable and Re-programmable

• When Security Bit Set:

– Data Verification Disabled

– Data Transfer to FPSLIC not Externally Visible

– Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip Erase

• When Security Bit Cleared:

– Entire Chip Erase Performed

– In-System Programming Enabled

– Data Verification Enabled

External Data pins allow for In-System Programming of the device and setting of the EEPROM-

based security bit. When the security bit is set (active) this programming connection will only

respond to a device erase command. Data cannot be read out of the external programming/data

pins when the security bit is set. The part can be re-programmed, but only after first being

erased.

4. Programming and Configuration Timing Characteristics

Atmel’s Configurator Programming Software (CPS), available from the Atmel web site

(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the programming

algorithm for the embedded configurator; however, if you are planning to write your own soft-

ware or use other means to program the embedded configurator, the section below includes the

algorithm and other details.

4.1

The FPSLIC Configurator

The FPSLIC Configurator is a serial EEPROM memory which is used to load programmable

devices. This document describes the features needed to program the Configurator from within

its programming mode (i.e., when SER_EN is driven Low).

Reference schematics are supplied for ISP applications.

4.2

Serial Bus Overview

The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided by the

programmer, the second wire (cSDA) is a bi-directional signal and is used to provide data and

control information.

Information is transmitted on the serial bus in messages. Each MESSAGE is preceded by a

Start Condition and ends with a Stop Condition. The message consists of an integer number of

bytes, each byte consisting of 8 bits of data, followed by a ninth Acknowledge Bit. This Acknowl-

edge Bit is provided by the recipient of the transmitted byte. This is possible because devices

AT94S Secure Family

2314E–FPSLI–6/05

AT94S Secure Family

may only drive the cSDA line Low. The system must provide a small pull-up current (1 kΩ equiv-

alent) for the cSDA line.

The MESSAGE FORMAT for read and write instructions consists of the bytes shown in

“Bit For-

mat” on page 5.

While writing, the programmer is responsible for issuing the instruction and data. While reading,

the programmer issues the instruction and acknowledges the data from the Configurator as

necessary.

Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte-by-

byte basis.

The factory blanks devices to all zeros before shipping. The array cannot otherwise be “initial-

ized” except by explicitly writing a known value to each location using the serial protocol

described herein.

4.3

Bit Format

Data on the cSDA pin may change only during the cSCK Low time; whereas Start and Stop Con-

ditions are identified as transitions during the cSCK High time.

Write Instruction Message Format

START

DEVICE

CONDITION ADDRESS

MS EEPROM

(NEXT) EEPROM

LS EEPROM

DATA

ADDRESS BYTE ADDRESS BYTE ADDRESS BYTE BYTE 1

STOP

DATA

BYTE n CONDITION

ACK BIT

(CONFIGURATOR)

Current Address Read (Extended to Sequential Read) Instruction Message Format

START

CONDITION

DEVICE

ADDRESS

DATA

BYTE 1

DATA

BYTE n

STOP

CONDITION

ACK BIT

(CONFIGURATOR)

ACK BIT

(PROGRAMMER)

4.4

Start and Stop Conditions

The Start Condition is indicated by a high-to-low transition of the cSDA line when the cSCK line

is High. Similarly, the Stop Condition is generated by a low-to-high transition of the cSDA line

when the cSCK line is High, as shown in

Figure 4-1.

The Start Condition will return the device to the state where it is waiting for a Device Address (its

normal quiescent mode).

The Stop Condition initiates an internally timed write signal whose maximum duration is t

(refer to AC Characteristics table for actual value). During this time, the Configurator must

remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines are ignored

until the cycle is completed. Since the write cycle typically completes in less than t

seconds,

we recommend the use of “polling” as described in later sections. Input levels to all other pins

should be held constant until the write cycle has been completed.

2314E–FPSLI–6/05

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