M21012/M21011/M21001
Quad Multi-Rate CDR (42 Mbps - 3.2 Gbps)
The M21012 is a high-performance quad multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom, and datacom
applications. Each channel has an independent multi-rate CDR capable of operating at data-rates between 42 Mbps and 3.2 Gbps,
allowing maximum flexibility in system design. The M21011 is rated for operation in the range of 1 Gbps to 3.2 Gbps. The M21001 is
rated for operation in the range of 42 Mbps to 800 Mbps. Aside from the difference in supported signal data-rates, the M21012, M21011,
and M21001 are identical. Signal conditioning features include input equalization and output pre-emphasis, allowing robust reception
and transmission of signals to other devices up to 60" away. User-selectable input interface types allow DC-coupled input to CML, LVDS,
and LVPECL. The outputs can also be DC-coupled to CML and LVDS. Frequency acquisition is accomplished with an external reference
clock. The built-in frequency synthesizer allows multi-rate operation, while operating with a single reference clock. The device can be
controlled either through hardwired pins or an I
2
C -compatible interface. The hardwired mode eliminates the need for an external micro-
controller, while allowing control of the key features of the device. The I
2
C-compatible interface allows complete control of the device fea-
tures.
Applications
•
•
•
•
•
•
Backplane reach extension
SONET OC-48, OC-48 with FEC systems and modules
Fibre Channel systems
Gigabit Ethernet systems
10GBASE-CX4 systems and modules
Clock Synthesizer
Features
• M21012 has four independent Multi-Rate CDRs capable of running
between 42 Mbps and 3.2 Gbps
• M21011 has four independent Multi-Rate CDRs capable of running
between 1 Gbps and 3.2 Gbps
• M21001 has four independent Multi-Rate CDRs capable of running
between 42 Mbps and 800 Mbps
• Flexible DC-Coupled input interface to CML, LVPECL, and LVDS
• Flexible Control through I
2
C-compatible interface or hardwired pins
• Jitter generation 4.5 mUI rms, Jitter Tolerance 0.625 UI typical
• Signal conditioning features for superior performance on FR4 trace
lengths of up to 60", twinaxial cable lengths of up to 25m
• Typical Total Power Consumption as low as 400 mW with all channels
running
• Built-in pattern generator and receiver for module and system testing
Functional Block Diagram
CTRL_Mode
[1:0]
Out_Mode
[1:0]
xLOA
[3:0]
xLOL
[3:0]
xJTAG_En
MF
[11:0]
Multifunction Pin Array
Serial Interface/Hardwired Mode
Din0
[P/N]
JTAG
Voltage
Regulator
Cout0
[P/N]
Cout1
[P/N]
Cout2
[P/N]
Cout3
[P/N]
Dout0
[P/N]
Dout1
[P/N]
Dout2
[P/N]
Dout3
[P/N]
Adapative Input Equalization
Din1
[P/N]
Din2
[P/N]
Din3
[P/N]
BIST Tx
BIST Rx
VddT0/1
210xx-DSH-001-D
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
RefClk
[P/N]
VddT2/3
BIST Rx Mux
Selectable CML, LVDS
Output Buffer +
Pre-Emphasis
Universal Input Buffer
BIST Transmitter Mux
CDR Array
xRegu_En
xRST
November 2005
Ordering Information
Part Number
M21012-12
M21012G-12
(1)
M21011-12
M21011G-12
(1)
M21001-12
M21001G-12
(1)
Package
72-terminal, 10mm, MLF
72-terminal, 10mm, MLF
(RoHS compliant)
72-terminal, 10mm, MLF
72-terminal, 10mm, MLF
(RoHS compliant)
72-terminal, 10mm, MLF
72-terminal, 10mm, MLF
(RoHS compliant)
Operating Data Rate
42 Mbps - 3.2 Gbps
42 Mbps - 3.2 Gbps
1 Gbps - 3.2 Gbps
1 Gbps - 3.2 Gbps
42 Mbps - 800 Mbps
42 Mbps - 800 Mbps
NOTES:
1. The letter “G” designator after the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional
information.
2. M21012, M21011, M21001 are the base device numbers, and -12 is the device revision number.
3. These devices are shipped in trays.
Revision History
Revision
D
Level
Release
Date
November 2005
Description
• Discontinued support for LVPECL output interface.
• Added note about reserved two-wire serial interface addresses 00001xx.
• Updated
Table 2-1
with absolute maximum ratings for high-speed signal, control,
interface, and alarm pins.
• Added RoHS compliant part numbers to the ordering information.
•
Table 2-2
note 4 updated to reflect 0°C
≤
T
a
≤
70°C for F
VCO
> 2.666 GHz.
• Added
Section 1.2.15
to provide details on supported ambient temperature range as a
function of data-rate.
• Included figure “Definition of Pre-Emphasis Levels” in
Section 1.2.11
• Inserted eye diagrams in
Section 1.2.10
showing input equalization performance.
C
Release
July 2005
210xx-DSH-001-D
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
ii
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
1.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Detailed Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.1
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.3
Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.4
High-Speed Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.5
CDR Reference Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2.6
Multifunction Pins Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2.7
Multifunction Pins Defined for Hardwired Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2.8
Two-Wire Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.9
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2.10 Input Deterministic Jitter Attenuators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2.11 Output Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.2.12 CDR Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.2.13 Multi-Rate CDR Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2.14 Frequency Reference Acquisition (FRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2.15 Ambient Temperature Range Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.2.16 Loss of Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.2.17 Built-In Self Test (BIST) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.2.18 BIST Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.2.19 BIST Receiver (BIST Rx) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.2.20 BIST Transmitter (BIST Tx) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.2.21 Junction Temperature Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2.22 IC Identification / Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.3
2.0
Product Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1
2.2
2.3
2.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Input/Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
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iii
2.5
2.6
2.7
CDR Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Package Drawings and Surface Mount Assembly Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PCB High-Speed Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.0
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1
Global Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.1.1
Global Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.1.2
External Reference Frequency Divider Control (RFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.1.3
Master IC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.1.4
IC Electronic Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.1.5
IC Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.1.6
Built In Self-Test (BIST) Receiver Channel Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.1.7
Built In Self-Test (BIST) Receiver Main Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.1.8
Built In Self-Test (BIST) Receiver Bit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.1.9
Built In Self-Test (BIST) Transmitter Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.1.10 Built In Self-Test (BIST) Transmitter Main Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.1.11 Built In Self-Test (BIST) Transmitter PLL Loss of Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.1.12 Built In Self-Test (BIST) Transmitter PLL Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.1.13 Built In Self-Test (BIST) Transmitter PLL Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.1.14 Built In Self-Test (BIST) Transmitter PLL Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.1.15 Built In Self-Test (BIST) Transmitter 20 bit User Programmable Pattern . . . . . . . . . . . . . . . . . . . . . . . . .52
3.1.16 Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern . . . . . . . . . . . . . . . . . . . . . .53
3.1.17 Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern . . . . . . . . . . . . . . . . . . . . . .53
3.1.18 Built In Self-Test (BIST) Transmitter Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.1.19 Internal Junction Temperature Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.1.20 Internal Junction Temperature Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.1.21 CDR Loss of Lock Register Alarm Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.1.22 Loss of Activity Register Alarm Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Individual Channel/CDR Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.2.1
CDR N Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.2.2
CDR N Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.2.3
CDR N Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.2.4
Output Buffer Control for CDR N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.2.5
Output Buffer Pre-Emphasis Control for Output N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.2.6
Input Equalization Control for Output N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.2.7
CDR N Loop Bandwidth and Data Sampling Point Adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.2.8
CDR N FRA LOL Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.2.9
Jitter Reduction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.2
4.0
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1
4.2
Glossary of Terms/Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.2.1
External . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.2.2
Mindspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
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iv
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Module Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Backplane Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Recommended Data and Reference Clock Input Coupling Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
STS-48 waveform after transmission through 76” of PCB traces (input to M21012) . . . . . . . . . . . . . .10
STS-48 waveform at M21012 output with input shown in Figure 1-4 . . . . . . . . . . . . . . . . . . . . . . . . .10
Definition of Pre-Emphasis Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Block Diagram of FRA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
M21012 Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Data Input Internal Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Reference Clock Input Internal Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clock to Data Output Skew Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Jitter Tolerance Specification Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Jitter Transfer Specification Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Cross-Section of MLF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
68-Pin Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
72-Pin Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PCB Footprint for 72-Pin 10 mm MLF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PCB Pad Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Recommended Via Array for Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Trace-Length Matching Using Serpentine Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Loop Length Matching for Differential Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
210xx-DSH-001-D
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
v
京公网安备 11010802033920号
EEWORLD
