EP1SGX25FF1020I7N datasheet, PDF

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EP1SGX25FF1020I7N: DescriptionField Programmable Gate Array, 25660-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020; CategoryProgrammable logic devices Programmable logic; File Size4MB，279 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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EP1SGX25FF1020I7N Overview

Field Programmable Gate Array, 25660-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020

EP1SGX25FF1020I7N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
package instruction	33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B1020
JESD-609 code	e1
length	33 mm
Number of entries	607
Number of logical units	25660
Output times	607
Number of terminals	1020
Maximum operating temperature	135 °C
Minimum operating temperature	-65 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1020,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	245
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	33 mm

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Section I. Stratix GX

Device Family Data Sheet

This section provides the data sheet specifications for Stratix

devices. It contains feature definitions of the internal architecture,

configuration information, testing information, DC operating conditions,

and AC timing parameters.

This section includes the following chapters:

■

Chapter 1, Introduction to the Stratix GX Device Data Sheet

Chapter 2, Stratix GX Transceivers

Chapter 3, Source-Synchronous Signaling With DPA

Chapter 4, Stratix GX Architecture

Chapter 5, Configuration & Testing

Chapter 6, DC & Switching Characteristics

Chapter 7, Reference & Ordering Information

Revision History

The table below shows the revision history for

Chapters 1

through

Chapter(s)

Date / Version

February 2005, v1.0

August 2005, v1.1

February 2005, v1.0

August 2005, v1.1

February 2005, v1.0

Changes Made

Initial Release.

Added Note (3) to Figure 3-7.

Initial Release.

Updated Tables 6-7 and 6-50.

Initial Release.

Altera Corporation

Section I–1

Preliminary

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