SC3011B-1
•
•
•
•
•
Quartz SAW Frequency Stability
Fundamental Fixed Frequency
Very Low Jitter and Power Consumption
Rugged, Miniature, Surface-Mount Case
Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use with high-speed CPUs and digitizers. Fundamental-mode oscillation is
made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size,
and low power consumption. Differential outputs provide a sine wave that is capable of driving 50
Ω
loads.
600.0 MHz
Differential
Sine-Wave
Clock
Rating
Power Supply Voltage (V
CC
at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8 Case
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Absolute Frequency
Tolerance from 600.000 MHz
Voltage into 50Ω (VSWR≤1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Q and Q Period Jitter
Output (Disabled)
No Noise on V
CC
200 mV
P-P
from 1 MHz to ½ f
O
on
Amplitude into 50
Ω
V
IH
V
IL
I
IH
I
IL
t
PD
V
CC
I
CC
T
A
1, 3
1, 3
+3.13
0
+3.30
20
3, 9
Sym
f
O
Δf
O
V
O
Notes
1, 2
1, 3
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 4, 7, 8
3, 9
3
Minimum
599.850
0.60
49
Typical
Maximum
600.150
±250
1.1
2:1
51
Units
MHz
ppm
V
P-P
%
dBc
dBc
ps
P-P
ps
P-P
mV
P-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
-25
15
-20
-60
30
35
75
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
50
V
CC
-0.1
0.0
3
V
CC
V
CC
+0.1
0.20
5
-1
1
+3.47
40
+70
RFM SC3011B-1 600.00 MHz YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
2.
3.
4.
5.
6.
Unless otherwise noted, all specifications include any combination of load
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50
Ω
loads
to ground. (See: Typical Test Circuit.)
One or more of the following United States patents apply: 4,616,197;
4,670,681; 4,760,352.
The design, manufacturing process, and specifications of this device are
subject to change without notice.
Only under the nominal conditions of 50
Ω
load impedance with VSWR
≤
1.2 and nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
Jitter and other spurious outputs induced by externally generated electrical
noise on V
CC
or mechanical vibration are not included. Dedicated external
7.
8.
9.
voltage regulation and careful PCB layout are recommended for optimum
performance.
Applies to period jitter of Q and Q. Measurements are made with the
Tektronix CSA803 signal analyzer with at least 1000 samples.
Period jitter measured with a 200 mV
P-P
sine wave swept from 1 MHz to
one-half of f
O
at the V
CC
power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation
delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as
the fall time from the 50% point to the 10% point. (SEE: Timing
Definitions.)
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 1 of 2
SC3011B-1 - 3/27/08
Electrical Connections
Footprint
Actual size footprint:
1
8
7
6
5
Terminal
Number
1
2
3
4
5
6
7
8
LID
Connection
V
CC
Ground
NC or Ground
Q Output
Q Output
Ground
ENABLE
Ground
2
3
4
Typical Printed Circuit Board Land Pattern
TOP VIEW
A typical land pattern for a circuit board is shown below. Grounding of the
metallic center pad is optional.
Typically 0.01" to 0.05" or 0.25 mm to
1.25 mm (8 Places)
Case Design
All pads consist of 30 microinches (min) electroless gold on 50 microinches
(min) electroless nickel over base metal. The metallic center pad was
designed for mechanical support. Grounding of this pad is optional.
Lid symbolization, including terminal 1 locator dot, are in contrasting ink.
Symbolization varies by model number. For purposes of illustration, only
terminal 1 dot is shown.
(The optimum value of this dimension is
dependent on the PCB assembly process
employed.)
.
Typical Test Circuit
V
cc
0.1
μ
F
Sine-Wave
Signal Generator
B
C
D
E
4.7
μ
H
F
(X8)
N
(X8)
A
M
G
L
(X3)
V
cc
50
Ω
Q
50
Ω
Q
*
Tektronix
CSA 803
Digitizing
Oscilloscope
Ch 1
Trigger
Ch 2
Clock
Under Test
H
(X2)
*
ENABLE
50
Ω
*Power Splitter, Mini-Circuits ZFSC2-4
K
J
Timing Definitions
Propagation Delay:
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
Millimeters
Min
Max
13.46
9.14
13.97
9.66
Inches
Min
0.530
0.360
ENABLE
Max
0.550
0.380
50%
50%
2.05 Nominal
3.56 Nominal
2.24 Nominal
1.27 Nominal
2.54 Nominal
3.05 Nominal
1.93 Nominal
5.54 Nominal
4.32 Nominal
4.83 Nominal
0.50 Nominal
0.081 Nominal
0.141 Nominal
0.088 Nominal
0.050 Nominal
0.120 Nominal
0.120 Nominal
0.076 Nominal
0.218 Nominal
0.170 Nominal
0.190 Nominal
0.020 Nominal
Q or Q Output
Amplitude
Envelope
90%
10%
t
PD
Symmetry:
t
PD
Q or Q Output
50%
50%
50%
Symmetry as
% of Period
Period
Symmetry as
% of Period
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 2 of 2
SC3011B-1 - 3/27/08
京公网安备 11010802033920号
EEWORLD
