Low power timer circuit

Shown is a timing control circuit. This circuit uses NAND gate CD4011 and time base circuit NE555 to form a low-power timing
control circuit. In this circuit, an RS flip-flop composed of NAND gate CD4011 is used as an electronic switch. When Kl is closed and connected to the power supply,
the 100 kfl resistor and O.Ol yF capacitor make the YF2 input terminal in a low level state, that is, s=o, Rl of the RS flip-flop, then Q=o, and the YF1
output terminal is locked at low level. Level "0". Transistor 9013 is turned off. The monostable timer composed of NE555 does not work. At this time, the entire circuit
only has quiescent currents of 1-2 UA for YF1, YF2 and 9013. When K2 is pressed, a negative pulse is generated, causing YF1 to output high level and lock
. 9013 is turned on, NE555 is powered and begins to enter a temporary steady state. The @ pin of NE555 outputs high level, and relay J is closed. After a delay,
the temporary steady state ends, and NE555 returns to steady state. At this time, the output of pin ③ is low level and relay J is released. If you want the timer to work again, you should
cut off the power switch Kl, then close it, and then press K2. The contacts of the relay can be used to control other electrical components.