a
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp for YUV Applications
R
IN
CLAMP
Analog Interface for
Flat Panel Displays
AD9886
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
8
8
AD9886
8
A/D
R
OUTA
R
OUTB
G
OUTA
G
OUTB
8
G
IN
CLAMP
A/D
8
8
8
GENERAL DESCRIPTION
The AD9886 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports resolutions up to SXGA (1280
×
1024 at 75 Hz).
For ease of design and to minimize cost, the AD9886 is a fully
integrated interface solution for FPDs. The AD9886 includes a
140 MHz triple ADC with internal 1.25 V reference, PLL to
generate a pixel clock from an HSYNC, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and an HSYNC signal. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9886’s on-chip PLL generates a pixel clock from an
HSYNC. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of HSYNC. A sampling phase
adjustment is provided. Data, HSYNC and Clock output phase
relationships are maintained. The PLL can be disabled and an
external clock input provided as the pixel clock. The AD9886
also offers full sync processing for composite sync and sync-on-
green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a 2-wire serial interface.
B
IN
CLAMP
A/D
8
8
B
OUTA
B
OUTB
HSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SYNC
PROCESSING
AND CLOCK
GENERATION
2
DATACK
HSOUT
VSOUT
SOGOUT
REF
REFOUT
REFIN
SCL
SDA
A
1
A
0
SERIAL REGISTER AND
POWER MANAGEMENT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9886–SPECIFICATIONS
(V = 3.3 V, V
D
DD
= 3.3 V, ADC Clock = Maximum Conversion Rate.)
Min
AD9886KS-140
Typ
Max
8
+1.15/–1.0
+1.15/–1.0
±
1.4
±
1.75
±
0.5
±
0.5
Guaranteed
+1.25/–1.0
+1.25/–1.0
±
1.65
±
2.5
Unit
Bits
LSB
LSB
LSB
LSB
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
Temp
Test
Level
Min
AD9886KS-100
Typ
Max
8
25°C
Full
25°C
Full
Full
I
VI
I
VI
VI
±
0.5
±
0.5
Guaranteed
Full
Full
25°C
25°C
Full
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
VI
0.5
1.0
135
1
1
50
8.0
56
1.0
150
0.5
7
44
50
7
44
50
1
1
50
8.0
56
V p–p
V p–p
ppm/°C
µA
µA
mV
% FS
% FS
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
1
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew, t
SKEW
t
BUFF
t
STAH
t
DHO
t
DAL
t
DAH
t
DSU
t
STASU
t
STOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Current, High (V
IH
)
Input Current, Low (V
IL
)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle
DATACK,
DATACK
Output Coding
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
VI
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
IV
IV
V
VI
VI
IV
1.20
1.25
±
50
1.30
1.20
1.25
±
50
1.30
V
ppm/°C
MSPS
MSPS
ns
µs
µs
µs
µs
µs
µs
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
100
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100
400
10
+2.0
140
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
400
10
+2.0
110
12
700
2
1000
2
110
12
700
3
1000
3
15
2.5
0.8
–1.0
1.0
3
V
D
– 0.1
0.1
45
50
Binary
55
45
V
D
– 0.1
2.5
15
ps/°C
V
V
µA
µA
pF
V
V
%
0.8
–1.0
1.0
3
0.1
50
Binary
55
–2–
REV. 0
AD9886
Parameter
POWER SUPPLY
V
D
Supply Voltage
V
DD
Supply Voltage
P
VD
Supply Voltage
I
D
Supply Current (V
D
)
I
DD
Supply Current (V
DD
)
4
IP
VD
Supply Current (P
VD
)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
Temp
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Test
Level
IV
IV
IV
V
V
V
VI
VI
VI
V
V
V
V
V
V
AD9886KS-100
Min
Typ
Max
3.0
2.2
3.0
3.3
3.3
3.3
140
34
15
564
13
43
330
2
1.5
46
45
60
3.6
3.6
3.6
AD9886KS-140
Min
Typ
Max
3.0
2.2
3.0
3.3
3.3
3.3
155
48
16
715
13
43
330
2
1.5
46
45
60
3.6
3.6
3.6
Unit
V
V
V
mA
mA
mA
mW
mA
mW
MHz
ns
ns
dB
dB
dBc
850
25
82.5
850
25
82.5
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
5
(Without Harmonics)
f
IN
= 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θ
JC
Junction-to-Case
Thermal Resistance
θ
JA
Junction-to-Ambient
Thermal Resistance
V
V
20
40
20
40
°C/W
°C/W
NOTES
1
Drive Strength = 11.
2
VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.
3
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.
4
DEMUX = 1, DATACK and
DATACK
Load = 10 pF, Data Load = 5 pF.
5
Using external pixel clock.
Specifications subject to change without notice.
REV. 0
–3–
AD9886
ABSOLUTE MAXIMUM RATINGS*
V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I
100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing.
ORDERING GUIDE
Model
AD9886KS-140
AD9886KS-100
AD9886/PCB
Temperature
Range
0°C to 70°C
0°C to 70°C
25°C
Package
Description
Plastic Quad Flatpack
Plastic Quad Flatpack
Evaluation Board
Package
Option
S-160
S-160
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9886 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9886
PIN CONFIGURATION
147
RED A<3>
146
RED A<4>
145
RED A<5>
136
S
CDT
135
DATACLKB
160
RED B<0>
159
RED B<1>
158
RED B<2>
157
RED B<3>
156
RED B<4>
155
RED B<5>
154
RED B<6>
153
RED B<7>
150
RED A<0>
149
RED A<1>
148
RED A<2>
144
RED A<6>
143
RED A<7>
134
DATACLK
140
SOGOUT
126
REF
OUT
125
REF
IN
124
VD
138
VSOUT
129
SCAN
IN
128
GND
139
HSOUT
152
GND
142
GND
133
GND
131
GND
130
GND
122
GND
VDD
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
VDD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
VDD
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
VDD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
121
GND
151
VDD
141
VDD
137
NC
132
VDD
127
VD
123
VD
120
PIN 1
IDENTIFIER
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
AD9886
TOP VIEW
(Not to Scale)
RMIDSCV
R
AIN
RCLAMPV
VD
GND
VD
VD
GND
GND
GMIDSCV
G
AIN
GCLAMPV
SOGIN
VD
GND
VD
VD
GND
GND
BMIDSCV
B
AIN
BCLAMPV
VD
GND
VD
GND
CKINV
CLAMP
SDA
SCL
A0
A1
PVD
PVD
GND
GND
COAST
CKEXT
HSYNC
VSYNC
NC = NO CONNECT
REV. 0
GND
GND
VDD
GND
SCAN
OUT
NC
NC
NC
NC
SCAN
CLK
VD
GND
NC
VD
VD
NC
NC
GND
NC
NC
GND
NC
NC
GND
NC
NC
VD
VD
GND
VD
NC
NC
NC
GND
PVD
GND
PVD
FILT
PVD
GND
–5–
京公网安备 11010802033920号
EEWORLD
