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BUK108-50DL

Description
PowerMOS transistor Logic level TOPFET
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size65KB,10 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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BUK108-50DL Overview

PowerMOS transistor Logic level TOPFET

BUK108-50DL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeMODULE
package instructionSSO-3
Contacts3
Reach Compliance Code_compli
ECCN codeEAR99
Built-in protectionTRANSIENT; OVER VOLTAGE; THERMAL
Interface integrated circuit typeBUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 codeX-XSSO-G3
JESD-609 codee3
Number of functions1
Number of terminals3
Package body materialUNSPECIFIED
Package shapeUNSPECIFIED
Package formSMALL OUTLINE
Certification statusNot Qualified
Nominal supply voltage5 V
surface mountYES
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal locationSINGLE
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 3 pin plastic surface
mount envelope, intended as a
general purpose switch for
automotive systems and other
applications.
BUK108-50DL
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
D
T
j
R
DS(ON)
I
ISL
PARAMETER
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
Input supply current
V
IS
= 5 V
MAX.
50
13.5
40
150
125
650
UNIT
V
A
W
˚C
mΩ
µA
APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Lower operating input current
permits direct drive by
micro-controller
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V
CLAMP
INPUT
RIG
POWER
MOSFET
LOGIC AND
PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT404
PIN
1
2
3
mb
input
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
D
TOPFET
I
P
2
1
3
S
June 1996
1
Rev 1.000
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