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74AHC573BQ,115

Description
Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R
Categorylatch   
File Size696KB,19 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric Compare View All

74AHC573BQ,115 Overview

Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R

74AHC573BQ,115 Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)EAR99
Part StatusActive
HTS8542.39.00.01
TypeD-Type
Logic FamilyAHC
Latch ModeTransparent
Number of Channels per Chip8
Number of Elements per Chip1
Number of Inputs per Chip8
Number of Input Enables per Element1
Number of Selection Inputs per Element0
Number of Outputs per Chip8
Number of Output Enables per Element1
Bus HoldNo
Set/ResetNo
PolarityNon-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns)14.5@3.3V|8.8@5V
Absolute Propagation Delay Time (ns)19.5
Process TechnologyCMOS
Output Type3-State
Maximum Low Level Output Current (mA)8
Maximum High Level Output Current (mA)-8
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)5
Maximum Operating Supply Voltage (V)5.5
Maximum Quiescent Current (uA)4
Propagation Delay Test Condition (pF)50
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
PackagingTape and Reel
Supplier PackageDHVQFN EP
Pin Count20
Standard Package NameQFN
MountingSurface Mount
Package Height0.88
Package Length4.5
Package Width2.5
PCB changed20
Lead ShapeNo Lead
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
Rev. 7 — 8 November 2011
Product data sheet
1. General description
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring
separate D-type inputs for each latch and 3-state true outputs for bus oriented
applications. A latch enable input (LE) and an output enable input (OE) are common to all
latches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
Dn input changes. When pin LE is LOW, the latches store the information that is present
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but
has a different pin arrangement.
2. Features and benefits
Balanced propagation delays
All inputs have a Schmitt trigger action
Common 3-state output enable input
Functionally identical to the 74AHC373; 74AHCT373
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC573: CMOS input level
For 74AHCT573: TTL input level
ESD protection:
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C

74AHC573BQ,115 Related Products

74AHC573BQ,115 74AHC573D,118 74AHC573D,112 74AHC573PW,118
Description Latch Transparent 3-ST 8-CH D-Type 20-Pin DHVQFN EP T/R Latch Transparent 3-ST 8-CH D-Type 20-Pin SO T/R Latch Transparent 3-ST 8-CH D-Type 20-Pin SO Bulk Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R
EU restricts the use of certain hazardous substances Compliant Compliant Compliant Compliant
ECCN (US) EAR99 EAR99 EAR99 EAR99
Part Status Active Active LTB Active
HTS 8542.39.00.01 8542.39.00.01 8542.39.00.01 8542.39.00.01
Type D-Type D-Type D-Type D-Type
Logic Family AHC AHC AHC AHC
Latch Mode Transparent Transparent Transparent Transparent
Number of Channels per Chip 8 8 8 8
Number of Elements per Chip 1 1 1 1
Number of Inputs per Chip 8 8 8 8
Number of Input Enables per Element 1 1 1 1
Number of Outputs per Chip 8 8 8 8
Number of Output Enables per Element 1 1 1 1
Bus Hold No No No No
Set/Reset No No No No
Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting
Maximum Propagation Delay Time @ Maximum CL (ns) 14.5@3.3V|8.8@5V 8.8@5V|14.5@3.3V 14.5@3.3V|8.8@5V 8.8@5V|14.5@3.3V
Absolute Propagation Delay Time (ns) 19.5 19.5 19.5 19.5
Process Technology CMOS CMOS CMOS CMOS
Output Type 3-State 3-State 3-State 3-State
Maximum Low Level Output Current (mA) 8 8 8 8
Maximum High Level Output Current (mA) -8 -8 -8 -8
Minimum Operating Supply Voltage (V) 2 2 2 2
Typical Operating Supply Voltage (V) 5 5 5 5
Maximum Operating Supply Voltage (V) 5.5 5.5 5.5 5.5
Maximum Quiescent Current (uA) 4 4 4 4
Propagation Delay Test Condition (pF) 50 50 50 50
Minimum Operating Temperature (°C) -40 -40 -40 -40
Maximum Operating Temperature (°C) 125 125 125 125
Packaging Tape and Reel Tape and Reel Bulk Tape and Reel
Supplier Package DHVQFN EP SO SO TSSOP
Pin Count 20 20 20 20
Mounting Surface Mount Surface Mount Surface Mount Surface Mount
Package Height 0.88 2.45(Max) 2.45(Max) 0.95(Max)
Package Length 4.5 13(Max) 13(Max) 6.6(Max)
Package Width 2.5 7.6(Max) 7.6(Max) 4.5(Max)
PCB changed 20 20 20 20
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