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AGL600V2-FGG256

Description
Field Programmable Gate Array, 13824 CLBs, 600000 Gates, 108MHz, CMOS, PBGA256
CategoryProgrammable logic devices    Programmable logic   
File Size6MB,264 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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AGL600V2-FGG256 Overview

Field Programmable Gate Array, 13824 CLBs, 600000 Gates, 108MHz, CMOS, PBGA256

AGL600V2-FGG256 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instruction17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-256
Reach Compliance Codecompli
Revision 27
DS0095
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X
,
and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
High Capacity
• 15K to 1 Million System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM
®
-enabled IGLOO
®
devices) via
JTAG (IEEE 1532–compliant)
• FlashLock
®
Designed to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in IGLOO FPGAs
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
IGLOO Devices
AGL015
1
ARM-Enabled IGLOO Devices
2
System Gates
15,000
Typical Equivalent Macrocells
128
VersaTiles (D-flip-flops)
384
Flash*Freeze Mode (typical, µW)
5
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits (1,024 bits)
1
2
AES-Protected ISP
3
Integrated PLL in CCCs
6
VersaNet Globals
4
I/O Banks
2
Maximum User I/Os
49
Package Pins
UC/CS
QFN
VQFP
FBGA
QN68
• M1 IGLOO Devices—Cortex
®
-M1 Soft Processor Available with
or without Debug
AGL030
30,000
256
768
5
1
6
2
81
AGL060 AGL125
60,000
512
1,536
10
18
4
1
Yes
1
18
2
96
125,000
1,024
3,072
16
36
8
1
Yes
1
18
2
133
CS196
QN132
6
VQ100
FG144
AGL250
M1AGL250
250,000
2,048
6,144
24
36
8
1
Yes
1
18
4
143
CS196
5
QN132
6
VQ100
FG144
AGL400
400,000
9,216
32
54
12
1
Yes
1
18
4
194
CS196
AGL600
M1AGL600
600,000
13,824
36
108
24
1
Yes
1
18
4
235
CS281
AGL1000
M1AGL1000
1,000,000
24,576
53
144
32
1
Yes
1
18
4
300
CS281
UC81, CS81 CS121
3
QN48, QN68,
QN132
6
QN132
6
VQ100
VQ100
FG144, FG256, FG144, FG256, FG144, FG256,
FG484
FG484
FG484
Notes:
1.
2.
3.
4.
5.
6.
7.
AGL015 is not recommended for new designs
AES is not available for ARM-enabled IGLOO devices.
AGL060 in CS121 does not support the PLL.
Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
The M1AGL250 device does not support this package.
Package not available.
The
IGLOOe
datasheet and
IGLOOe FPGA Fabric User Guide
provide information on higher densities and additional features.
† AGL015 and AGL030 devices do not support this feature.
May 2016
© 2016 Microsemi Corporation
‡ Supported only by AGL015 and AGL030 devices.
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