Standard Products
UT7R2XLR816 Clock Network Manager
Datasheet
April, 2015
www.aeroflex.com/Clocks
FEATURES:
+3.3V
Core Power Supply
Independent
power supply for each clock bank
- Power supply range from +2.25V to +3.6V
8
Output clock banks with flexible I/O signaling
- Up to 16 LVCMOS3.3 outputs with
12mA slew-rate limited, break-before-make, buffers, or
- Up to 16 LVCMOS2.5 outputs with
8mA slew-rate limited, break-before-make, buffers, or
- Up to 8 standard drive LVDS outputs
Temperature
range:
- Commercial: 0
o
C to +70
o
C
- Industrial: -40
o
C to +85
o
C
- HiRel: -55
o
C to +125
o
C
Operational environment:
- Total-dose: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm
2
/mg
- SEU Immune to a LET of 109 MeV-cm
2
/mg
Packaging
options
(1.27mm pitch, 17mm sq. body):
- 168-CLGA
- 168-CBGA
- 168-CCGA
Input
clock multiplication of any integer from 1 - 32
PLL
Operation
- Low frequency range: 24MHz to 50MHz
- Mid frequency range: 48MHz to 100MHz
- High frequency range: 96MHz to 200MHz
Input
reference clock signaling and control:
- LVCMOS3.3/LVTTL (Cold-Spared),
LVDS (Cold-Spared), &
Parallel Resonant Quartz Crystal
- Reference input divide-by-1 or divide-by-2
- Input frequency range from 2MHz to 200MHz
Dedicated
feedback Input/Output module
- Independent feedback power supply (+3.0V to +3.6V)
- 1-to-32 divider options with/without inverting
- Phase control -6, -4, -3, -2, -1, 0, 1, 2, 3, 4, 6 tU
- Disabled HIGH-Z when RST/DIV = LOW
- No Synchronous Output Enable (sOE) control in order to main-
tain PLL lock
Standard Microcircuit Drawing 5962-08243
- QML Q and Q+
Applications
- High altitude avionics
- X-ray Cargo Scanners
- Test and Measurement
- Networking, telecommunications and mass storage
INTRODUCTION:
The UT7R2XLR816 is a low voltage, low power, clock network
manager. The device features 16-outputs in 8 banks of 2.
Independent power supplies for each bank (+2.25V to +3.6V)
give the user great flexibility in multi- voltage systems. Outputs
can be configured as LVCMOS (2.5V/8mA or 3.3V/12mA) or
standard LVDS pairs. Independent output bank division and
phase skewing empower the system designer to optimize output
phase and frequency relationships throughout a clock network.
The skew controls enable outputs to lead or lag the reference
clock while the ternary output divider control can divide the
PLL oscillator frequency by any integer from 1to 32 before
driving the clock out of the desired bank. Regardless of output divider
settings, input and output clock edges are synchronized at start-up and
whenever the device is removed from power down mode. Power
down mode is controlled by the RST/DIV ternany input which also
controls input division of the reference clock. Time units for skew
control (t
U
) are 22.5
o
of the clock cycle for low and mid frequency
oscillators and 45
o
of the clock cycle for the high frequency oscillator.
Output
clock bank signaling and control:
- Output frequency range from 750KHz to 200MHz
- 1-to-32 divider options with/without inverting
- Odd bank phase control -4, -3, -2, -1, 0, 1, 2, 3, 4 tU
- Even bank phase control -6, -4, -2, -1, 0, 1, 2, 4, 6 tU
- Disable HIGH, LOW, or HIGH-Z
- Synchronous Output Enable (sOE) control
Guaranteed
reference input to output edge
synchronization
Low
inherent output bank skew (e.g. SKEW = 0*tU)
- < 50ps intrabank skew (typical)
- < 100ps interbank skew without dividing or inverting (typ)
- < 250ps interbank skew across divided or inverted banks (typ)
1
Slew rate optimization of outputs is determined by the PLL oscillator
range selected and thus is controlled by the FREQ_SEL input. Output
rise times decrease as higher frequency range oscillators are selected.
The input reference clock can be LVCMOS/LVTTL/ LVDS or a
quartz crystal. The LVCMOS/LVTTL and LVDS inputs are cold-
spared. Input reference frequencies can range from 2MHz to
200MHz. Using the RST/DIV pin and FB_DS[3:0] feedback divider
settings for the reference clock can be multiplied by 0.5x-32x in steps
of 0.5 through a multiplication factor of 16 and integer steps for mul-
tiplication factors 17 through 32.
To provide further clock network optimization, the feedback
output bank includes independent skew and division control.
PLL lock is identified by the active high LOCK signal. LOCK will
only become true when the REFERENCE and FB_IN clocks are sta-
ble and aligned to within t
LOCKRES
, which is variable based on the
state of the FREQ_SEL pin. At all other times, LOCK will remain
LOW.
Clock outputs are deterministic in that if either the reference input
clock or feedback clock are absent, the outputs will oscillate at a fre-
quency near the midpoint of the selected PLL operating range.
Test modes are available for user diagnostics. The TEST ternary input
enables the test modes. When TEST is low, normal operation occurs.
Floating the TEST pin to a mid-range value disables the PLL oscilla-
tors and drives the clock output banks with the REF clock input. Set-
ting TEST high disables the PLL oscillators and drives the clock
output banks with the FB_IN input.
2
L2
J2
J1
B2
K2
H3
J4
K3
FB_PS1
Phase Select
K11
H1
FB_PS0
FB_DS0
FB_DS1
FB_DS2
FREQ_SEL
FB_DS3
F2
RST#/DIV
3-Lvl
R-Div
RST#
(N-divider)
Divide by
1-to-32
& Invert
G1
C1
D1
M1
L1
F3
REF
LVDIN+_
LVDIN-_
XTAL_IN
XTAL_OUT
REF_SEL
2-Lvl
2-Lvl
2-Lvl
2-Lvl
2-Lvl
3-Lvl
2-Lvl
(R-Divider)
Reference
Clock
Select
Phase –
Frequency
Detector
CTRL
3-Lvl
VCO
3-Lvl
3-Lvl
LVCMOS
Feedback
Output
FB_OUT
3-Lvl
PLL
24MHZ – 200MHz
LOCK
M6
M5
L5
M4
M2
L3
K6
L7
K8
L8
L6
K5
K10
L10
L11
M10
M9
L9
H11
F10
F11
G11
H12
J11
E11
C12
D11
F12
L12
J10
D8
C11
C9
B9
D10
C10
B10
C7
B4
D6
C8
B8
C5
C3
D7
B5
B6
C6
0Q_DS3
0Q_DS2
0Q_DS1
0Q_DS0
0Q_PS1
0Q_PS0
1Q_DS3
1Q_DS2
1Q_DS1
1Q_DS0
1Q_PS1
1Q_PS0
2Q_DS3
2Q_DS2
2Q_DS1
2Q_DS0
2Q_PS1
2Q_PS0
3Q_DS3
3Q_DS2
3Q_DS1
3Q_DS0
3Q_PS1
3Q_PS0
4Q_DS3
4Q_DS2
4Q_DS1
4Q_DS0
4Q_PS1
4Q_PS0
5Q_DS3
5Q_DS2
5Q_DS1
5Q_DS0
5Q_PS1
5Q_PS0
6Q_DS3
6Q_DS2
6Q_DS1
6Q_DS0
6Q_PS1
6Q_PS0
7Q_DS3
7Q_DS2
7Q_DS1
7Q_DS0
7Q_PS1
7Q_PS0
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 0 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 1 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 2 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 3 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 4 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 5 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 6 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
3-Lvl
Divide by 1-to-32
& Invert
3-Lvl
3-Lvl
Bank 7 Clock Control
3-Lvl
Phase Select
3-Lvl
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
0Q0
FB_PS2
FB_IN
TEST
K4
D4
N4
0Q1
N3
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
1Q0
N8
1Q1
N7
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
2Q0
N12
2Q1
N11
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
3Q0
J13
3Q1
K13
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
4Q0
D13
4Q1
E13
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
5Q0
A11
5Q1
A12
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
6Q0
A7
6Q1
A8
3-Lvl
LVCMOS/
LVDS
DRIVERS
3-Lvl
3-Lvl
2-Lvl
7Q0
A3
7Q1
A4
sOE#
CM#/LV
D9
H10
Figure 1. UT7R2XLR816 Block Diagram
3
1.0 Functional Description
The UT7R2XLR816, clock network manager, has an array of
special features designed to overcome many of the clock
management and clock distribution challenges common in
today’s high-performance electronic systems. This section of
the datasheet provides an overview of the primary features
within and is intended to acquaint the designer with their basic
capabilities.
Although discussed in more detail below, the user should
understand that many features within the UT7R2XLR816 are
selected by ternary control signals. These ternary controls
recognize three separate logic levels on a single pin. The
L(ow) state means that the control input pin is driven below
the V
ILL
level specified in the DC electrical table of this
datasheet. Conversely, a H(igh) means that the control input is
driven above the V
IHH
voltage described in the DC electrical
table. While a M(id) state requires that the input pin be floated,
allowing the internal resistor divider network to place the pin
into a level compliant with the V
IMM
voltage listed in the DC
electrical table, or externally driven/biased to the V
IMM
level.
1.1 Reference Clocks
The UT7R2XLR816 is capable of receiving its reference
clock from one of three sources. The REF input allows for
a single ended, LVTTL/LVCMOS clock source. The
LVDIN+ and LVDIN- pins combine to receive an LVDS
reference clock. The LVDIN+ should be driven by the
positive half of the LVDS clock signal while the LVDIN-
should be driven by the negative half of the LVDS clock
signal. A 100 terminating resistor should be connected
directly between the LVDIN+ and LVDIN- terminals.
Finally, the XTAL_IN and XTAL_OUT terminals
provide for a quartz crystal resonator reference clock
input. The XTAL_IN pin is the input to the on-chip pierce
oscillator and should be connected directly to one side of
an external quartz crystal that is tuned to operate in the
parallel resonance mode. The XTAL_OUT pin drives out
the 180° phase shifted version of the reference clock
received on XTAL_IN. The XTAL_OUT pin should drive
the other end of the external quartz crystal resonator
circuit. Reference figure 3 for an example quartz crystal
oscillator circuit.
The REF, LVDIN+ and LVDIN- inputs are cold-spared.
The cold-sparing capability of these reference pins make
them ideal for receiving an off-board clock source that
may be active while the UT7R2XLR816 is unpowered.
The UT7R2XLR816 provides a ternary reference select
pin (REF_SEL) that is used to control which of the three
available clock sources the UT7R2XLR816 will use as its
timing reference. Since REF_SEL ensures that only one
reference source can drive the internal circuitry of the
UT7R2XLR816 the remaining two clock sources may be
driven simultaneously allowing the REF_SEL pin to
select between these reference sources. As mentioned
above, REF_SEL is a ternary, or three level input. Setting
REF_SEL L(ow) selects the XTAL_IN/XTAL_OUT
crystal resonator source. Placing REF_SEL into a M(id)
level (left floating), sets the REF input as the
UT7R2XLR816 reference clock source. Finally, driving
REF_SEL H(igh), enables the LVDS (LVDIN+/LVDIN-)
clock source. These available REF_SEL configurations
are shown in figures 2, 3 and 4.
1.2 Feedback Clock
The UT7R2XLR816 contains a dedicated feedback I/O
module that is completely separate from the eight (8)
output clock banks. The FB_IN feedback input can be
driven directly from the FB_OUT pin, or from a digital
circuit having the FB_OUT pin as its source.
The FB_IN signal connects to the internal Phase-
Frequency Detector (PFD), which compares the FB_IN
signal with the clock reference source as selected by the
REF_SEL control. Phase shifts associated with board
trace delays from routing, in-line circuitry, or intentional
phase skewing within the feedback path are adjusted by
the PFD to advance or delay the Phase-Locked Loop
(PLL), as necessary, to ensure that the clock arriving at
FB_IN is phase aligned with the selected reference clock
source.
The FB_OUT is an LVCMOS3 output signal driven by
the PLL. As discussed in Tables 1 and 2, the frequency
and phase of the FB_OUT signal may be adjusted by the
FB_DS[3:0] output divider settings and the FB_PS[2:0]
phase selection settings, respectively. Both pin groups,
FB_DS[3:0] and FB_PS[2:0], are ternary inputs. The
FB_DS[3:0] settings are used to multiply the frequency of
the internal PLL by dividing the frequency of the
FB_OUT signal.
FB_OUT may be divided by any integer from 1 to 32, as-
well-as inverted following the division operation.
Inversion provides a 180° phase shift of the PLL from the
4
incoming reference source, effectively synchronizing the
PLL to the opposite edge of the reference clock. To ensure
stable locking of the PLL and to free the output clock
banks to drive the system clock, FB_OUT should always
be used as the originating clock source for the FB_IN pin.
The FB_PS[2:0] feedback phase selection pins allow the
FB_OUT signal to be phase shifted by -6, -4, -3, -2, -1, 0,
1, 2, 3, 4, or 6 tu (time units). The value of tu is
determined by the FREQ_SEL setting and the PLL’s
operating frequency. Examples of tu calculation are
shown in Equation 1 and Table 5. Phase shifting FB_OUT
has the effect of advancing or delaying the PLL and, by
extension, the nominal phase of all output clock banks. A
positive phase shift (i.e. delay) in FB_OUT advances the
PLL and clock output banks so they lead the reference
clock by the same phase shift amount. Conversely, a
negative shift (i.e. advancement) of FB_OUT causes the
PLL and output clock banks to lag the reference clock
source by the same amount of phase shift.
1.3 Phase-Locked Loop (PLL) and Frequency Generation
The UT7R2XLR816’s PLL circuitry consists of the
previously mentioned reference and feedback input clock
sources, a Phase–Frequency Detector (PFD), and a
Voltage-Controlled Oscillator (VCO). The voltage
controlled oscillator consists of three separate oscillators
that are optimized to run in three specific frequency
bands. The ternary FREQ_SEL input is used to select the
appropriate VCO based upon the nominal PLL frequency
required by the application. The nominal PLL frequency
range selected by FREQ_SEL are 24 – 50MHz
(FREQ_SEL=Low), 48 – 100MHz (FREQ_SEL=Mid)
and 96 – 200MHz (FREQ_SEL=High).
The UT7R2XLR816 includes an internal reset signal to
ensure that the selected VCO starts-up and the PLL
establishes lock with the stable reference clock sources
whenever power is applied to the device, or the device is
dynamically reconfigured to select a different VCO.
However, Aeroflex recommends that dynamic
reconfiguration be performed while the device is held in
RESET (e.g. RST/DIV=Low) to ensure a smooth re-start
and avoid uncontrolled behavior from the device during
the reconfiguration process.
An additional start-up feature provided by the
UT7R2XLR816 is the inclusion of a PLL pre-charge
circuit that places the selected VCO into a mid-band
frequency of operation in the event that either one, or
both, of the reference and feedback clocks are removed or
drop to a frequency below f
REFDET
. The intent of this
feature is to ensure that the PLL demonstrates
deterministic behavior if the device is out of reset and the
PFD does not receive valid, stable, input clocks. By
controlling the active VCO when the PFD does not have a
valid set of input clocks to compare ensures that any
active output clock bank oscillates at a manageable
frequency for downstream electronics. It is also
recommended that the sOE pin be used in conjunction
with the UT7R2XLR816 startup by disabling the output
banks until the device has completed its PLL locktime
(tLOCK) and the LOCK output is stable high.
When valid, stable, reference and feedback clocks are
available to the PFD, it will override the pre-charge
circuitry and begin to control the VCO. Although the PFD
works to maintain frequency and phase alignment
between the reference and FB_IN to an ideal 0ns
difference, it will inform the user that the PLL is locked
onto the incoming clocks when they are phase aligned to
within 2ns (typical) for the low and mid VCO selections,
and within 1.5ns (typical) for the high VCO. When this
condition is met, the UT7R2XLR816 will drive the LOCK
output high, indicating to the system the PLL is locked.
When the LOCK pin is LOW, the PLL is not locked and
the clock outputs may not be stable or synchronized to the
reference clock source. The LOCK will de-assert LOW
when the reference clock and the FB_IN are separated by
greater than the defined alignments, unless the device is
reset.
5
stm32/stm8
京公网安备 11010802033920号
EEWORLD
