MG802C256QR-6R6 datasheet, PDF

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MG802C256QR-6R6: DescriptionMemory IC; Categorystorage storage; File Size318KB，20 Pages; ManufacturerMonolithic System Technology Inc

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MG802C256QR-6R6 Overview

Memory IC

MG802C256QR-6R6 Parametric

Parameter Name	Attribute value
Maker	Monolithic System Technology Inc
package instruction	,
Reach Compliance Code	unknow
ECCN code	EAR99

MG802C256QR-6R6 Preview

MG802C256

Ultra Low Latency, High Performance

256Kx32 SGRAM

Preliminary Information

Features

•

SGRAM protocol

High bandwidth 100MHz-166MHz operation

Reduced Latency

Improved critical timing parameter limits

2 Internal Banks for hiding Row Precharge

Independent byte operation via DQM[3:0]

Burst length - 1,2,4,8 and full page

Burst Type: Linear, Wrap

Capacity: 8Mb

Organization: 256Kx32 (8Mbit)

Refresh Interval 15.6uSec

CBR Refresh.

LVTTL Interface

Supply voltages - 3.3 V

0.3V

Package - 100-pin QFP

Overview

The M

SGRAM is a synchronous memory for graphics, multimedia, networking and other

applications. It implements SGRAM commands and offers shorter Precharge (t

), faster Access

Latency (t

, t

RAS

, t

RCD

and CL=2) and better pipelining capability. In addition to the SGRAM

command set, the M

SGRAM implements an eight column Block Write function and a

Masked Write (Write Per Bit) function to accommodate graphics applications.

Options

MoSys SGRAM supports the following device options

Option

6.0ns Cycle Time

6.6ns Cycle Time

7.5ns Cycle Time

8ns Cycle Time

10ns Cycle Time

Marking

-6

-6R6

-7R5

-8

-10

Part Number Designation

Example:

MG802C256QR -8

Device Designation:

MG8

, Series:

02C

Organization:

256Kx32

Package Type:

=PQFP,

=LQFP

Pinout:

Reverse (Mirror Image)

Speed:

– 8

=125MHz

Key Timing Parameters

Speed

Grade

-6

-6R6

-7R5

-8

-10

Clock

Frequency

(MHz)

166

150

133

125

100

Access

Time

(ns)

Setup

Time

(ns)

2.2

2.3

2.5

Hold

Time

(ns)

CAS

Latency

(CL)

RAS Access

Time - tRAS

(ns)

26.4

Cycle Time -

tRC

(ns)

46.2

DS06, Rev 1.1 - 01/26/98

Preliminary Information

Page 1

MG802C256

Ultra Low Latency, High Performance

256Kx32 SGRAM

Preliminary Information

Functional Description

Pin Description

Name

CLK

CS#

CKE

Pin Number

Total

I/O

Description

A[8:0]

RAS#

CAS#

WE#

DSF

DQM[3:0]

51-47, 34-31

57, 24, 56, 23

DQ[31:0]

84, 83, 81, 80,

78, 77, 75, 74,

1, 20, 18, 17,

13, 12, 10, 9,

72, 71, 69, 68,

64, 63, 61, 60,

7, 6, 4, 3, 1,

100, 98, 97

I/O

System Clock:

All inputs are sampled on positive edge.

Chip select:

Disables or enables the device operation by

masking or enabling all inputs except CLK, CKE and DQM.

Clock Enable:

CKE controls the Power Down Mode in

SGRAM. When in Power Down Mode all input and

output buffers are de-activated.

Address Inputs:

Row & Column address are multiplexed on

the same pins.

Row Address Strobe:

Latches Row address on the positive

edge of clock with RAS# low. Enables Row access.

Column Address Strobe:

Latches Column Address on the

positive edge of clock. Enables column access.

Write Enable:

Enables write operation.

DSF:

Enables the Write Per Bit and Block Write function.

This pin has an internal pull-down resistor.

Data Input/Output Mask:

Write data byte mask, Read

output byte enables. Read latency is two cycle from DQM

and zero cycle for write. The DQM masking occurs two

cycles later in the Read operation and in the same cycle

during Write operation. DQM is synchronous to the clock,

thus the masking occurs for the whole clock.

Data Input/Output:

Bidirectional data bus.

Bank Address 0:

Bank Address defines to which Bank the

Activate, Read, Write or Precharge Command is issued.

BA0 is also used to program the 10 bit of the Mode

Signal description for 256Kx32 MoSys SGRAM

Input

Parameter

Bank Address

Row Address

A[8:0]

Column Address

A[7:0]

Auto Precharge

Page Size

256x32

Bank, Row and Column Address mapping

DS06, Rev 1.1 - 01/26/98

Preliminary Information

Page 2

MG802C256

Ultra Low Latency, High Performance

256Kx32 SGRAM

Preliminary Information

CONTROL REGISTERS

SGRAM incorporates four programmable registers, the Mode Select Register (MSR),

Special Mode Register (SMR), Color Register (CR) and the Mask Register (MR). This section

describes the use of these registers. In describing the functionality, the following terms are used.

Write Only.

A register bit with this attribute is Write Only.

Reserved.

A register bit with this attribute is Reserved.

Mode Register (MSR)

SGRAM’s mode register is accessed through the Mode Register Write Command (op

code ‘00000’). Mode Register is used to load the value of CAS Latency and Burst Length of

SGRAM.

Bit

8:7

Default

Attribute

Description

Reserved:

6:4

011

Standard operation

Reserved (for M

Use only)

Reserved (for M

Use only)

Reserved (for M

Use only)

CAS Latency:

000

Reserved

001

Reserved

010

011

100

101

Reserved

110

Reserved

111

Reserved

Burst Type:

0=Linear Burst Mode, 1=Wrap Mode

Burst Length:

BT=0

BT=1

000

001

010

011

100

Reserved

101

Reserved

110

Reserved

111

Full Page

Reserved

Description of Mode Register

2:0

010

DS06, Rev 1.1 - 01/26/98

Preliminary Information

Page 3

MG802C256

Ultra Low Latency, High Performance

256Kx32 SGRAM

Preliminary Information

Special Mode Register (SMR)

SGRAM’s Special Mode Register is accessed through the Mode Register Read/Write

Command (op code ‘00001’). Special Mode Register is used to load data into the Color Register

or the Mask register. During the execution of the Special Mode Register Command Bits A[6:5]

are used to determine if a new value is to be loaded into the Color and Mask Registers.

Bit

BA0, A[8:7]

A[6]

A[5]

A[4:0]

Default

000

0000

Attribute

Description

Reserved:

For Standard operation these bits should always be

“000”.

Color Register:

0=Leave data unchanged for Color Register,

1=Load new data into Color Register.

Mask Register:

0=Leave data unchanged for Mask Register,

1=Load new data into Mask Register.

Reserved:

For Standard operation these bits should always

be “0000”.

Description of Special Mode Register

Color Register (CR)

Data is loaded into the Color Register through the Special Mode Register Write Command. During

the execution of the Special Mode Register Command, bit A[6] is used to determine if a new

value is to be loaded into the Mask Registers. If A[6] =1 during the Special Mode Register

Command then the value on DQ[31:0] is loaded into the Color Register. The Color Register

supplies data for the Block Write Command.

Bit

31:0

Default

00000000h

Attribute

Description

Color Register Data:

Data from these bits is used for Block

Write Command.

Description of Color Register

Mask Register (MR)

Data is loaded into the Mask Register through the Special Mode Register Write Command.

During the execution of the Special Mode Register Command, bit A[5] is used to determine if a

new value is to be loaded into the Mask Registers. If A[5] =1 during the Special Mode Register

Command then the value on DQ[31:0] is loaded into the Mask Register. The Mask Register is

used for Mask Per Bit functionality during the Masked Write of Masked Block Write Command.

Mask Per Bit is used in conjunction with the DQM[3:0] to determine the mask for each bit.

Bit

31:0

Default

00000000h

Attribute

Description

Mask Register Data:

Data from these bits is used for Masked

Write and Block Write Command.

Description of Mask Register

DS06, Rev 1.1 - 01/26/98

Preliminary Information

Page 4

MG802C256

Ultra Low Latency, High Performance

256Kx32 SGRAM

Preliminary Information

DEVICE OPERATION

This section provides a description of M

SGRAM device.

Device Function

The following command table lists all supported M

SGRAM commands. All fixed length burst

(non full page burst length) operations can be self terminated, terminated by BST, interrupted by

another Read or Write operation or by a Precharge operation to the same Bank. For Auto

Precharge Read or Write, the operation cannot be interrupted and has to self-terminate after the

programmed burst length. Auto Precharge has no effect for a full page burst length operation. To

provide backward compatibility with SDRAM command set, the M

SGRAM incorporates an

internal pull-down resistor for the DSF pin.

Mode Register Write

The Mode Register stores data for controlling various functions of M

SGRAM. Through the

mode register the CAS Latency, Burst Type, Burst Length and the PLL enable mode can be

programmed for the device. The default value of the Mode Register is defined as CAS Latency of

3, Burst Type of linear and Burst Length of 4. The Mode Register is written to by driving CS#,

RAS#, CAS#, WE# and DSF low.

Special Mode Register Write

The Special Mode Register controls the data written to Color or Mask Register of M

SGRAM. During the Special Mode Register Command A[6:5] are used to indicate to the M

SGRAM whether a new data pattern is to be written to Color or Mask Registers. The Special

Mode Register is written to by driving CS#, RAS#, CAS#, WE# and DSF high.

Bank Activate

The Bank Activate Command selects a Row in a Bank. Bank is activated by driving CS# low,

RAS# low, CAS# high, WE# high and DSF low with the correct Bank and Row specified on BA

and A[8:0]. The Read/Write Command can follow the Activate Command after the t

RCD

timing has

been met. Every Bank Activate Command must satisfy the minimum t

RAS

before a Precharge

Command can be issued to that Bank.

Activate with WPB

The Bank Activate with WPB Command selects a random Row in an idle Bank. Bank is activated

by driving CS# low, RAS# low, CAS# high, WE# high and DSF high with the correct Bank and

Row specified on A[10/9:0]. The Write or Block Write Command can follow the Activate

Command after the t

RCD

timing has been met. A Write Command to the selected Bank will be

masked according to the contents of the Mask Register and DQM[3:0]. A Block Write Command

following the Activate with WPB Command will be masked according to the contents of the Mask

Read

The Read Command is used to access data from an active Row and Bank within the device. The

Read Command is issued by driving CS# low, RAS# high, CAS# low, WE# high and A8 low (no

DS06, Rev 1.1 - 01/26/98

Preliminary Information

Page 5

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MG802C256QR-6R6 Related Products

	MG802C256QR-6R6	MG802C256LR-6	MG802C256LR-7R5	MG802C256LR-10	MG802C256QR-8	MG802C256QR-6	MG802C256QR-7R5
Description	Memory IC	Memory IC	Memory IC	Memory IC	Memory IC	Memory IC	Memory IC
Maker	Monolithic System Technology Inc	Monolithic System Technology Inc	Monolithic System Technology Inc	Monolithic System Technology Inc	Monolithic System Technology Inc	Monolithic System Technology Inc	Monolithic System Technology Inc
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknown

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