EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

VJ05006-BP681AGZCJ

Description
CAPACITOR, CERAMIC, MULTILAYER, 50 V, BP, 0.00068 uF, SURFACE MOUNT, 0805, CHIP
CategoryPassive components    capacitor   
File Size76KB,4 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Download Datasheet Parametric View All

VJ05006-BP681AGZCJ Overview

CAPACITOR, CERAMIC, MULTILAYER, 50 V, BP, 0.00068 uF, SURFACE MOUNT, 0805, CHIP

VJ05006-BP681AGZCJ Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerVishay
package instruction, 0805
Reach Compliance Codeunknown
ECCN codeEAR99
capacitance0.00068 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee0
Manufacturer's serial numberVJ
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance2%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR, EMBOSSED PLASTIC, 7 INCH
positive tolerance2%
Rated (DC) voltage (URdc)50 V
size code0805
surface mountYES
Temperature characteristic codeBP
Temperature Coefficient30ppm/Cel ppm/°C
Terminal surfaceTin/Lead (Sn/Pb)
Terminal shapeWRAPAROUND
The Principle and Application of 32-Channel 16-Bit D/A Converter MAX5631
Abstract: This paper introduces the basic functions of MAX5631, a 32-channel 16-bit D/A converter produced by MAXIM, USA. Its three working modes and working timing are discussed in detail. A serial i...
fighting Analog electronics
[SAMR21 New Gameplay] 24. Usage of I2C
[i=s]This post was last edited by dcexpert on 2019-10-14 09:14[/i]In CircuitPython, I2C, SPI, UART and other functions are provided by the busio module, so you need to import busio before you can use ...
dcexpert MicroPython Open Source section
Compilation warning issues
I wrote a program for CPLD to drive HT1621 and defined a function. But there is a warning when compiling. Warning (10241): Verilog HDL Function Declaration warning at ht1621.v(530): function "HT1621_C...
chenbingjy FPGA/CPLD
AD17 There is a problem with copper laying on a four-layer board
Dear teachers,I drew a four-layer board and laid copper, and the following two problems occurred. Can you give me a solution? 1 For the same GND network, some boxes have no copper, while others can in...
dmyhq PCB Design
Static Timing Analysis Basics and Applications
...
至芯科技FPGA大牛 FPGA/CPLD
Cost-effective 0-10V analog signal isolation technology: based on Y capacitor isolation
The 0-10V analog signal is converted into a modulated signal by the APC chip GP9301M, and then transmitted to the PAC chip GP8101M after passing through the isolation capacitor. The GP8101M demodulate...
zjqmyron Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号