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PHT2010H6980WG

Description
RESISTOR, THIN FILM, 0.1 W, 0.05 %, 100 ppm, 698 ohm, SURFACE MOUNT, 2010, CHIP, GREEN
CategoryPassive components    The resistor   
File Size106KB,6 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance  
Download Datasheet Parametric View All

PHT2010H6980WG Overview

RESISTOR, THIN FILM, 0.1 W, 0.05 %, 100 ppm, 698 ohm, SURFACE MOUNT, 2010, CHIP, GREEN

PHT2010H6980WG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVishay
package instructionSMT, 2010
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresHIGH PRECISION
structureChip
JESD-609 codee4
Manufacturer's serial numberPHT
Installation featuresSURFACE MOUNT
Number of terminals2
Maximum operating temperature215 °C
Minimum operating temperature-55 °C
Package height0.5 mm
Package length5.08 mm
Package shapeRECTANGULAR PACKAGE
Package formSMT
Package width2.54 mm
method of packingWAFFLE PACK
Rated power dissipation(P)0.1 W
resistance698 Ω
Resistor typeFIXED RESISTOR
seriesPHT
size code2010
surface mountYES
technologyTHIN FILM
Temperature Coefficient100 ppm/°C
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
Tolerance0.05%
Operating Voltage300 V
PHT
Vishay Sfernice
High Precision Wraparound - High Temperature (230 °C)
Thin Film Chip Resistors
FEATURES
Operating temperature range:
- 55 °C; + 215 °C
Storage temperature: - 55 °C; + 230 °C
Gold terminations (< 1 µm thick)
4 sizes available (0603, 0805, 1206, 2010) -
other sizes upon request
INTRODUCTION
For applications such as down hole applications, the need for
parts able to withstand very severe conditions (temperature
as high as 215 °C powered or up to 230 °C un-powered) has
leaded Vishay Sfernice to push out the limit of the thin film
technology.
Designers might read the application note: Power
Dissipation Considerations in High Precision Vishay Sfernice
Thin Film Chip Resistors and Arrays (P, PRA etc…) (High
Temperature Application)
www.vishay.com/doc?53047
in
conjunction with this datasheet to help them to properly
design their PCBs and get the best performances of the PHT.
Vishay Sfernice R&D engineers will be willing to support any
customer design considerations.
Temperature coefficient down to 25 ppm
(- 55 °C; + 215 °C)
Tolerance down to 0.05 %
Load life stability: 0.5 % max after 1000 h at 215 °C
(ambient) at Pn
SMD wraparound
Compliant to RoHS directive 2002/95/EC
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
A
CASE
SIZE
MAX. TOL.
+ 0.152 (+ 0.006)
MIN. TOL.
- 0.152 (- 0.006)
NOMINAL
0603
0805
1206
2010
1.52 (0.060)
1.91 (0.075)
3.06 (0.120)
5.08 (0.200)
B
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
NOMINAL
0.85 (0.033)
0.38 (0.015)
1.27 (0.050)
1.60 (0.063)
2.54 (0.100)
0.5 (0.02)
± 0.127 (0.005)
0.13 (0.005)
0.40 (0.016)
0.48 (0.019)
D/E
C
NOMINAL
TOLERANCE
** Please see document “Vishay Material Category Policy”:
www.vishay.com/doc?99902
www.vishay.com
1
For technical questions, contact:
sfer@vishay.com
Document Number: 53050
Revision: 10-Aug-10
05 Serial port experience and receiving variable-length data
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