FQD9N08L / FQU9N08L
December 2000
QFET
FQD9N08L / FQU9N08L
80V LOGIC N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize
on-state
resistance,
provide
superior
switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for low voltage applications such as automotive,
high efficiency switching for DC/DC converters, and DC
motor control.
TM
Features
•
•
•
•
•
•
•
•
7.4A, 80V, R
DS(on)
= 0.21Ω @V
GS
= 10 V
Low gate charge ( typical 4.7 nC)
Low Crss ( typical 16 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
Low level gate drive requirements allowing
direct operation from logic drives
D
D
!
"
G
!
G
S
! "
"
"
D-PAK
FQD Series
I-PAK
G D S
FQU Series
!
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
C
= 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25°C)
Drain Current
- Continuous (T
C
= 100°C)
Drain Current
- Pulsed
(Note 1)
FQD9N08L / FQU9N08L
80
7.4
4.68
29.6
±
20
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
A
= 25°C) *
Power Dissipation (T
C
= 25°C)
55
7.4
2.5
6.5
2.5
25
0.2
-55 to +150
300
T
J
, T
STG
T
L
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
Thermal Characteristics
Symbol
R
θJC
R
θJA
R
θJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
5.0
50
110
Units
°C/W
°C/W
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQD9N08L / FQU9N08L
Electrical Characteristics
Symbol
Parameter
T
C
= 25°C unless otherwise noted
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
∆BV
DSS
/
∆T
J
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
V
GS
= 0 V, I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 80 V, V
GS
= 0 V
V
DS
= 64 V, T
C
= 125°C
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
80
--
--
--
--
--
--
0.08
--
--
--
--
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Forward Transconductance
V
DS
= V
GS
, I
D
= 250
µA
V
GS
= 10 V, I
D
= 3.7 A
V
GS
= 5 V, I
D
= 3.7 A
V
DS
= 25 V, I
D
= 3.7 A
(Note 4)
1.0
--
--
--
0.15
0.17
4.8
2.0
0.21
0.23
--
V
Ω
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
--
--
215
70
16
280
90
20
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 64 V, I
D
= 9.3 A,
V
GS
= 5 V
(Note 4, 5)
V
DD
= 40 V, I
D
= 9.3 A,
R
G
= 25
Ω
(Note 4, 5)
--
--
--
--
--
--
--
6.5
180
13
30
4.7
1.2
2.8
23
370
35
70
6.1
--
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
V
GS
= 0 V, I
S
= 7.4 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0 V, I
S
= 9.3 A,
dI
F
/ dt = 100 A/µs
(Note 4)
--
--
--
--
--
--
--
--
54
80
7.4
29.6
1.5
--
--
A
A
V
ns
nC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 1.38mH, I
AS
= 7.4A, V
DD
= 25V, R
G
= 25
Ω,
Starting T
J
= 25°C
3. I
SD
≤
9.3A, di/dt
≤
300A/µs, V
DD
≤
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width
≤
300µs, Duty cycle
≤
2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQD9N08L / FQU9N08L
Typical Characteristics
10
1
I
D
, Drain Current [A]
I
D
, Drain Current [A]
V
GS
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
Top :
10
1
150℃
0
10
0
10
25℃
-55℃
※
Notes :
1. V
DS
= 25V
2. 250μ Pulse Test
s
※
Notes :
1. 250μ Pulse Test
s
2. T
C
= 25℃
10
-1
10
-1
10
0
10
1
10
-1
0
2
4
6
8
10
V
DS
, Drain-Source Voltage [V]
V
GS
, Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.8
I
DR
, Reverse Drain Current [A]
R
DS(on)
[
Ω
],
Drain-Source On-Resistance
10
1
0.6
V
GS
= 5V
0.4
V
GS
= 10V
10
0
0.2
※
Note : T
J
= 25℃
150℃
25℃
※
Notes :
1. V
GS
= 0V
2. 250μ Pulse Test
s
0.0
0
5
10
15
20
25
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
I
D
, Drain Current [A]
V
SD
, Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
600
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
12
500
10
V
GS
, Gate-Source Voltage [V]
V
DS
= 40V
8
400
Capacitance [pF]
V
DS
= 64V
300
C
iss
C
oss
※
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
6
200
4
100
C
rss
2
※
Note : I
D
= 9.3A
0
-1
10
0
10
0
10
1
0
1
2
3
4
5
6
7
8
9
V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQD9N08L / FQU9N08L
Typical Characteristics
(Continued)
1.2
3.0
2.5
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
R
DS(ON)
, (Normalized)
Drain-Source On-Resistance
1.1
2.0
1.0
1.5
1.0
0.9
※
Notes :
1. V
GS
= 0 V
2. I
D
= 250
μ
A
0.5
※
Notes :
1. V
GS
= 5 V
2. I
D
= 3.7 A
0.8
-100
-50
0
50
100
o
150
200
0.0
-100
-50
0
50
100
o
150
200
T
J
, Junction Temperature [ C]
T
J
, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
8
10
2
Operation in This Area
is Limited by R
DS(on)
6
I
D
, Drain Current [A]
100
µ
s
10
1
1 ms
10 ms
DC
I
D
, Drain Current [A]
2
4
10
0
※
Notes :
1. T
C
= 25 C
2. T
J
= 150 C
3. Single Pulse
o
o
2
10
-1
10
0
10
1
10
0
25
50
75
100
125
150
V
DS
, Drain-Source Voltage [V]
T
C
, Case Temperature [
℃
]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
( t) , T h e r m a l R e s p o n s e
D = 0 .5
※
N o te s :
1 . Z
θ
J C
( t ) = 5 . 0
℃
/W M a x .
2 . D u ty F a c t o r , D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
θ
J C
( t )
10
0
0 .2
0 .1
0 .0 5
0 .0 2
0 .0 1
P
DM
s in g le p u ls e
θ
JC
10
Z
-1
t
1
t
2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
, S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
FQD9N08L / FQU9N08L
Gate Charge Test Circuit & Waveform
50KΩ
12V
200nF
300nF
Same Type
as DUT
V
DS
V
GS
Q
g
5V
Q
gs
Q
gd
V
GS
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
V
DS
V
GS
R
G
R
L
V
DD
V
DS
90%
5V
DUT
V
GS
10%
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Unclamped Inductive Switching Test Circuit & Waveforms
L
V
DS
I
D
R
G
10V
t
p
BV
DSS
1
2
--------------------
E
AS
= ---- L I
AS
2
BV
DSS
- V
DD
BV
DSS
I
AS
V
DD
I
D
(t)
V
DD
t
p
DUT
V
DS
(t)
Time
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
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