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5962H9651302QXC

Description
NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, BOTTOM-BRAZED, CERAMIC, DFP-14
Categorylogic    logic   
File Size116KB,7 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962H9651302QXC Overview

NAND Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, BOTTOM-BRAZED, CERAMIC, DFP-14

5962H9651302QXC Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionDFP, FL14,.3
Reach Compliance Codeunknow
ECCN code3A001.A.1.A
seriesACT
JESD-30 codeR-CDFP-F14
JESD-609 codee4
length8.626 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
Prop。Delay @ Nom-Su8 ns
propagation delay (tpd)15 ns
Certification statusQualified
Schmitt triggerNO
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.575 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose1M Rad(Si) V
width6.477 mm
UT54ACTS00E
Quadruple 2-Input NAND Gates
July, 2013
Datasheet
www.aeroflex.com/Logic
FEATURES
0.6mCRH CMOS process
- Latchup immune
High speed
Low power consumption
Wide power supply operating range of 3.0V to 5.5V
Available QML Q or V processes
14-pin flatpack
UT54ACTS00E - SMD - 5962-96513
PINOUT
14-Lead Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
DESCRIPTION
The UT54ACTS00E is a quadruple, two-input NAND gate.
The circuit performs the Boolean functions Y = AB or Y = A
+ B in positive logic.
The device is characterized over full military temperature range
of -55C to +125C.
FUNCTION TABLE
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
Y4
Y3
Y1
Y2
LOGIC SYMBOL
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
(6)
(8)
Y2
Y3
Y4
A1
B1
A2
B2
A3
B3
A4
B4
&
(3)
Y1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
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