RTAX2000S-LG1152EV datasheet, PDF

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RTAX2000S-LG1152EV: DescriptionField Programmable Gate Array, 21504 CLBs, 2000000 Gates, CMOS, CBGA1152, LGA-1152; CategoryProgrammable logic devices Programmable logic; File Size6MB，198 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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RTAX2000S-LG1152EV Overview

Field Programmable Gate Array, 21504 CLBs, 2000000 Gates, CMOS, CBGA1152, LGA-1152

RTAX2000S-LG1152EV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	LGA, LGA(UNSPEC)
Reach Compliance Code	compli
Other features	250000 ASIC GATES ALSO AVAILABLE
Combined latency of CLB-Max	1.11 ns
JESD-30 code	S-CBGA-N1152
length	35 mm
Configurable number of logic blocks	21504
Equivalent number of gates	2000000
Number of entries	684
Output times	684
Number of terminals	1152
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	21504 CLBS, 2000000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LGA
Encapsulate equivalent code	LGA(UNSPEC)
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-PRF-38535
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	35 mm

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v5.4

RTAX-S/SL RadTolerant FPGAs

Radiation Performance

•

SEU-Hardened Registers Eliminate the Need for Triple-

Module Redundancy (TMR)

– Immune to Single-Event Upsets (SEU) to LET

> 37

MeV-cm

/mg

– SEU Rate < 10

-10

Errors/Bit-Day in Worst-Case

Geosynchronous Orbit

Expected SRAM Upset Rate of <10

-10

Errors/Bit-Day with

Use of Error Detection and Correction (EDAC) IP (included)

with Integrated SRAM Scrubber

– Single-Bit Correction, Double-Bit Detection

– Variable-Rate Background Refreshing

Total Ionizing Dose Up to 300 krad (Si, Functional)

Single-Event Latch-Up Immunity (SEL) to LET

> 117 MeV-

/mg

TM1019 Test Data Available

Single Event Transient (SET) – No Anomalies up to 150

MHz

Leading-Edge Performance

•

High-Performance Embedded FIFOs

350+ MHz System Performance

500+ MHz Internal Performance

700 Mb/s LVDS Capable I/Os

•

Specifications

•

Up to 4 Million Equivalent System Gates or 500 k

Equivalent ASIC Gates

Up to 20,160 SEU-Hardened Flip-Flops

Up to 840 I/Os

Up to 540 kbits Embedded SRAM

Manufactured on Advanced 0.15

μm

CMOS Antifuse

Process Technology, 7 Layers of Metal

Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,

TM3015)

•

Processing Flows

•

B-Flow – MIL-STD-883B

E-Flow – Actel Extended Flow

EV-Flow – Class V Equivalent Flow Processing Consistent

with MIL-PRF 38535

Features

•

Single-Chip, Nonvolatile Solution

1.5 V Core Voltage for Low Power

Flexible, Multi-Standard I/Os:

– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI

– JTAG Boundary Scan Testing (as per IEEE 1149.1)

– Differential I/O Standards: LVPECL and LVDS

– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Hot-Swap Compliant with Cold-Sparing Support

(Except PCI)

Embedded Memory with Variable Aspect Ratio and

Organizations:

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

– ROM Emulation Capability

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability

Prototyping Options

•

Commercial

Axcelerator

Devices

for

Functional

Verification

RTAX-S PROTO Devices with Same Functional and Timing

Characteristics as Flight Unit in a Non-Hermetic Package

Low Priced Reprogrammable ProASIC

3 Option for

Functional Verification

•

RTAX-SL Low Power Option

•

Offers Approximately Half the Standby Current of the

Standard RTAX-S Device at Worst-Case Conditions

•

Table 1 •

RTAX-S/SL Family Product Profile

Device

Capacity

Equivalent System Gates

ASIC Gates

Modules

Combinatorial (C-cells)

Flip-Flops (maximum)

Embedded RAM/FIFO (without EDAC)

Core RAM Blocks

Core RAM Bits (K = 1,024)

Clocks (segmentable)

Hardwired

Routed

I/Os

I/O Banks

User I/Os (maximum)

I/O Registers

Package

CCGA/LGA

CQFP

RTAX250S/SL

250,000

30,000

1,408

2,816

54 k

198

744

624

208, 352

RTAX1000S/SL

1,000,000

125,000

6,048

12,096

162 k

418

1,548

624

352

RTAX2000S/SL

2,000,000

250,000

10,752

21,504

288 k

684

2,052

624, 1152

256, 352

RTAX4000S/SL

4,000,000

500,000

20,160

40,320

120

540 k

840

2,520

1272

352

May 2009

See the Actel website for the latest version of the datasheet.

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