APA1000-BG456C datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> APA1000-BG456C

APA1000-BG456C: DescriptionField Programmable Gate Array, 180MHz, 56320-Cell, CMOS, PBGA456, 1.27 MM PITCH, PLASTIC, BGA-456; CategoryProgrammable logic devices Programmable logic; File Size2MB，83 Pages; ManufacturerActel; Websitehttp://www.actel.com/

Download Datasheet Parametric View All

APA1000-BG456C Overview

Field Programmable Gate Array, 180MHz, 56320-Cell, CMOS, PBGA456, 1.27 MM PITCH, PLASTIC, BGA-456

APA1000-BG456C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	1.27 MM PITCH, PLASTIC, BGA-456
Reach Compliance Code	unknow
maximum clock frequency	180 MHz
JESD-30 code	S-PBGA-B456
JESD-609 code	e0
length	35 mm
Humidity sensitivity level	3
Number of entries	356
Number of logical units	56320
Output times	356
Number of terminals	456
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA456,26X26,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	2.5,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	35 mm

Preview

Download Datasheet

View All

v5.8

ProASIC

PLUS®

Flash Family FPGAs

Features and Benefits

High Capacity

Commercial and Industrial

•

75,000 to 1 Million System Gates

27 k to 198 kbits of Two-Port SRAM

66 to 712 User I/Os

300, 000 to 1 million System Gates

72 k to 198 kbits of Two Port SRAM

158 to 712 User I/Os

0.22 µm 4 LM Flash-Based CMOS Process

Live At Power-Up (LAPU) Level 0 Support

Single-Chip Solution

No Configuration Device Required

Retains Programmed Design during Power-Down/Up Cycles

Mil/Aero Devices Operate over Full Military Temperature

Range

3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military

temperature)

Two Integrated PLLs

External System Performance up to 150 MHz

The Industry’s Most Effective Security Key (FlashLock

)

Low Impedance Flash Switches

Segmented Hierarchical Routing Structure

Small, Efficient, Configurable (Combinatorial or Sequential)

Logic Cells

APA075

75,000

3,072

27 k

158

Yes

100, 144

208

–

144

APA150

150,000

6,144

36k

242

Yes

100

208

456

144, 256

APA300

300,000

8,192

72 k

290

Yes

–

208

456

144, 256

208, 352

APA450

450,000

12,288

108 k

344

Yes

–

208

456

144, 256, 484

APA600

600,000

21,504

126 k

454

Yes

–

208

456

256, 484, 676

208, 352

624

APA750

750,000

32,768

144 k

562

Yes

–

208

456

676, 896

High Performance Routing Hierarchy

•

Ultra-Fast Local and Long-Line Network

High-Speed Very Long-Line Network

High-Performance, Low Skew, Splittable Global Network

100% Routability and Utilization

Schmitt-Trigger Option on Every Input

2.5 V/3.3 V Support with Individually-Selectable Voltage and

Slew Rate

Bidirectional Global I/Os

Compliance with PCI Specification Revision 2.2

Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

Pin Compatible Packages across the ProASIC

PLUS

Family

PLL with Flexible Phase, Multiply/Divide and Delay

Capabilities

Internal and/or External Dynamic PLL Configuration

Two LVPECL Differential Pairs for Clock or Data Inputs

Flexibility with Choice of Industry-Standard Front-End Tools

Efficient Design through Front-End Timing and Gate Optimization

In-System Programming (ISP) via JTAG Port

SmartGen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150 MHz (typical)

I/O

Military

Reprogrammable Flash Technology

Unique Clock Conditioning Circuitry

Standard FPGA and ASIC Design Flow

ISP Support

SRAMs and FIFOs

Performance

•

Secure Programming

Low Power

Table 1 •

ProASIC

PLUS

Product Profile

Device

Maximum System Gates

Tiles (Registers)

Embedded RAM Bits (k=1,024 bits)

Embedded RAM Blocks (256x9)

LVPECL

PLL

Global Networks

Maximum Clocks

Maximum User I/Os

JTAG ISP

PCI

Package (by pin count)

TQFP

PQFP

PBGA

FBGA

CQFP

CCGA/LGA

Notes:

APA1000

1,000,000

56,320

198 k

712

Yes

–

208

456

896, 1152

208, 352

624

1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.

2. These packages are available only for Military/MIL-STD-883B devices.

June 2009

See the Actel website for the latest version of the datasheet.

ProASIC

PLUS

Flash Family FPGAs

Table of Contents

General Description

ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-47

1-49

1-51

1-53

Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53

Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76

Recommended Design Practice for V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77

Package Pin Assignments

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . 3-8

v5.8

Recommended Resources

IB31 internal functional block diagram and pin function diagram

Internal circuit principle of M50197

Self-locking liquid level detector circuit diagram

Telephone ringtone automatic adjustment circuit diagram

Using TC9148 to remotely control MCS-51 microcontroller circuit

Computer motherboard circuit diagram 820 1_60

High-definition pictures to understand the high-end precision HDI board PCB architecture: When hardware engineers first come into contact with multi-layer PCBs, they are involved in ordinary multi-layer and HDI PCB boards. Now, three-dimensional graphics are used to display the internal ar...; 众创捷-PCBA一站式 PCB Design

[Perf-V Evaluation] Build and apply Hummingbird open source SOC based on Perf-V development board: [i=s]This post was last edited by superstar_gu on 2021-3-16 20:09[/i]Pengfeng Technology provides the Hummingbird E203 open source SoC and test program for the Perf-V development board. This article i...; superstar_gu EE_FPGA Learning Park

【GD32307E-START】03- Schematic diagram of expansion board: Since I am in the industrial control industry, I basically work on RS485 interfaces and network ports. When I designed the schematic, I expanded the 485 interface, 2 CAN interfaces, 1 Ethernet interfa...; 申小林 GD32 MCU

Classification of DSP processors: Sitara ARM Microprocessors– The Sitara product platform includes high-performance ARM Cortex-A8 and ARM9-based embedded microprocessors ranging from 375MHz to 1.GHz, with future roadmap devices exceed...; Aguilera DSP and ARM Processors

When BLE meets MEMS——Device Selection: [i=s] This post was last edited by lb8820265 on 2018-12-11 21:52[/i] [align=left][font=微软雅黑] This time I will introduce the selection of BLE and MEMS. It is often said that choice is more important th...; lb8820265 ST - Low Power RF

Oracle laid off employees again, rumored to be N+6 compensation, some people received 1 million compensation: Source: csdnRecently, an Oracle employee revealed on a social platform that they are currently laying off employees with N+6 compensation.In fact, Oracle has been laying off employees in Beijing since...; eric_wang Talking

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components