DATASHEET
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
6P41302
Description
The 6P41302 is an 8-output very low power clock generator
for PCIe Gen1-2-3 applications with integrated output
terminations providing Zo = 100. The device has 8 output
enables for clock management and supports 2 different
spread spectrum levels in addition to spread off.
Features
•
Integrated terminations provide 100 differential Zo;
•
•
•
•
•
•
•
•
•
•
•
•
•
reduced component count and board space
1.8V operation; reduced power consumption
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 6 x 6 mm 48-VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Typical Applications
PCIe Gen1–3 Clock Generator for Freescale designs
Output Features
•
8 0.7V low-power HCSL-compatible (LP-HCSL) DIF
•
pairs with Zo = 100
1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•
•
•
•
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–3 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
DIF7
DIF6
DIF5
SS Capable PLL
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
8
REF1.8
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
1
6P41302
JANUARY 24, 2018
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Pin Configuration
^CKPWRGD_PD#
VDD1.8
VDDIO
VDDIO
vOE7#
vOE6#
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri
GNDXTAL
X1_25
X2
VDDXTAL1.8
VDDREF1.8
vSADR/REF1.8
GNDREF
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
1
2
3
4
5
6
7
8
9
10
11
12
vOE0#
DIF0
VDDIO
36
35
34
33
32
31
30
29
28
27
26
25
GND
DIF2
DIF2#
DIF5#
DIF5
vOE4#
DIF4#
DIF4
VDDIO
VDDA1.8
GNDA
vOE3#
DIF3#
DIF3
vOE2#
6P41302
13 14 15 16 17 18 19 20 21 22 23 24
DIF0#
vOE1#
DIF1
DIF1#
VDD1.8
VDDIO
48-VFQFPN, 6 x 6 mm, 0.4mm pitch
vv prefix indicates internal 60kOhm pull-down resistor
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
Pins 5, 6 and 12 are the Suspend voltage rails.
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OEx#
True O/P
Comp. O/P
OE bit
0
X
X
Low
Low
Hi-Z
1
1
1
0
Running
Running Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
5
6
12
20,38
30
13,21,31,39,
47
VDDIO
GND
2
8
9
22,29,40
29
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
2
vOE5#
DIF7#
DIF6#
GND
DIF7
DIF6
6P41302
JANUARY 24, 2018
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
PIN NAME
vSS_EN_tri
GNDXTAL
X1_25
X2
VDDXTAL1.8
VDDREF1.8
vSADR/REF1.8
GNDREF
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
vOE0#
DIF0
DIF0#
vOE1#
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
vOE2#
DIF3
DIF3#
vOE3#
GNDA
VDDA1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDD1.8
VDDIO
TYPE
LATCHED
IN
GND
IN
OUT
PWR
PWR
LATCHED
I/O
GND
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
DESCRIPTION
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND for XTAL
Crystal input, Nominally 25.00MHz.
Crystal output.
Power supply for XTAL, nominal 1.8V
VDD for REF output. nominal 1.8V.
Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
Ground pin for the REF outputs.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
Power supply for differential outputs
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
3
6P41302
JANUARY 24, 2018
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Pin Descriptions (cont.)
PIN #
PIN NAME
40 GND
41 DIF6
42 DIF6#
43
44
45
46
47
48
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
TYPE
GND
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
4
6P41302
JANUARY 24, 2018
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Device
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
3.3V
Driving LVDS
Cc
R7a
R7b
Rs
Zo
Cc
Rs
Device
R8a
R8b
LVDS Clock
input
Driving LVDS inputs with the 6P41302
Value
Receiver has Receiver does not
Component
termination
have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
5
6P41302
JANUARY 24, 2018
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