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6P41302NDGI8

Description
VFQFPN-48, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size515KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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6P41302NDGI8 Overview

VFQFPN-48, Reel

6P41302NDGI8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instruction6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, VFQFPN-48
Contacts48
Manufacturer packaging codeNDG48P1
Reach Compliance Codecompli
ECCN codeEAR99
JESD-30 codeS-XQCC-N48
JESD-609 codee3
length6 mm
Humidity sensitivity level3
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency25 MHz
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC48,.24SQ,16
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Master clock/crystal nominal frequency27 MHz
Certification statusNot Qualified
Maximum seat height1 mm
Maximum slew rate35 mA
Maximum supply voltage1.9 V
Minimum supply voltage1.7 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.4 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width6 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
DATASHEET
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
6P41302
Description
The 6P41302 is an 8-output very low power clock generator
for PCIe Gen1-2-3 applications with integrated output
terminations providing Zo = 100. The device has 8 output
enables for clock management and supports 2 different
spread spectrum levels in addition to spread off.
Features
Integrated terminations provide 100 differential Zo;
reduced component count and board space
1.8V operation; reduced power consumption
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 6 x 6 mm 48-VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Typical Applications
PCIe Gen1–3 Clock Generator for Freescale designs
Output Features
8 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs with Zo = 100
1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–3 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
DIF7
DIF6
DIF5
SS Capable PLL
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
8
REF1.8
IDT®
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
1
6P41302
JANUARY 24, 2018

6P41302NDGI8 Related Products

6P41302NDGI8 6P41302NDGI
Description VFQFPN-48, Reel VFQFPN-48, Tray
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code VFQFPN VFQFPN
package instruction 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, VFQFPN-48 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, VFQFPN-48
Contacts 48 48
Manufacturer packaging code NDG48P1 NDG48P1
Reach Compliance Code compli compli
ECCN code EAR99 EAR99
JESD-30 code S-XQCC-N48 S-XQCC-N48
JESD-609 code e3 e3
length 6 mm 6 mm
Humidity sensitivity level 3 3
Number of terminals 48 48
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Maximum output clock frequency 25 MHz 25 MHz
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN
Encapsulate equivalent code LCC48,.24SQ,16 LCC48,.24SQ,16
Package shape SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260
power supply 1.8 V 1.8 V
Master clock/crystal nominal frequency 27 MHz 27 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1 mm 1 mm
Maximum slew rate 35 mA 35 mA
Maximum supply voltage 1.9 V 1.9 V
Minimum supply voltage 1.7 V 1.7 V
Nominal supply voltage 1.8 V 1.8 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD
Terminal pitch 0.4 mm 0.4 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 6 mm 6 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
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