IS61C12816
128K x 16 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 12, 15, and 20 ns
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin SOJ package and
44-pin TSOP(II)
ISSI
®
DECEMBER 2000
DESCRIPTION
The
ISSI
IS61C12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using
ISSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields access times as fast as 12 ns with low power
consumption.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61C12816 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP
(II)
.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
1
IS61C12816
PIN CONFIGURATIONS
44-Pin SOJ
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
ISSI
44-Pin TSOP(II)
A15
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
®
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
OE
WE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
LB
UB
NC
Vcc
GND
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
Write
I
CC
1
, I
CC
2
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
IS61C12816
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
ISSI
®
Note:
1. Stress greater than those listed under ABSO-
LUTE MAXIMUM RATINGS may cause per-
manent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions above
those indicated in the operational sections of
this specification is not implied. Exposure to
absolute maximum rating conditions for ex-
tended periods may affect reliability.
1
2
3
4
5
OPERATING RANGE
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Speed
-12
-15, -20
-12
-15, -20
V
CC
5V ± 5%
5V ± 10%
5V ± 5%
5V ± 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND - V
IN
- V
CC
GND - V
OUT
- V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.5
–2
–2
Max.
—
0.4
V
CC
+ 0.5
0.8
2
2
Unit
V
V
V
V
µA
µA
6
7
8
9
Notes:
1. V
IL
(min.) = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
I
SB
1
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
• V
IH
, f = 0
V
CC
= Max.,
CE
• V
CC
– 0.2V,
V
IN
• V
CC
– 0.2V, or
V
IN
- 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-12
Min. Max.
280
—
—
—
—
—
—
300
50
55
10
15
-15
Min. Max.
260
—
—
—
—
—
—
290
50
55
10
15
-0
2
Min. Max.
235
—
—
—
—
—
mA
255
50
55
10
15
mA
Unit
10
11
mA
I
SB
2
12
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
3
IS61C12816
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
ISSI
®
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to High-Z Output
CE
to Low-Z Output
LB, UB
Access Time
LB, UB
to High-Z Output
LB, UB
to Low-Z Output
-12
Min. Max.
12
—
3
—
—
—
0
0
3
—
0
0
—
12
—
12
6
6
—
6
—
6
6
—
-15
Min. Max.
15
—
3
—
—
0
0
0
3
—
0
0
—
15
—
15
7
6
—
6
—
7
6
—
-20
Min. Max.
20
—
4
—
—
0
0
0
3
—
0
0
—
20
—
20
9
8
—
8
—
9
8
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
t
LZB
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
Ω
5V
480
Ω
5V
OUTPUT
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1
4
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
IS61C12816
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE =
OE
= V
IL
,
UB
or
LB
= V
IL
)
t
RC
ISSI
®
1
2
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
3
4
READ CYCLE NO. 2
(1,3)
t
RC
5
t
OHA
ADDRESS
t
AA
OE
t
DOE
t
HZOE
6
7
CE
t
LZCE
t
LZOE
t
ACE
t
HZCE
LB, UB
t
BA
t
HZB
DATA VALID
8
HIGH-Z
t
LZB
D
OUT
9
10
11
12
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE, UB,
or
LB
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transition.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
5
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