MT58V2MV18PF-10IT datasheet, PDF

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MT58V2MV18PF-10IT: DescriptionStandard SRAM, 2MX18, 5ns, CMOS, PBGA165; Categorystorage storage; File Size533KB，34 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT58V2MV18PF-10IT Overview

Standard SRAM, 2MX18, 5ns, CMOS, PBGA165

MT58V2MV18PF-10IT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Reach Compliance Code	unknow
Maximum access time	5 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
memory density	37748736 bi
Memory IC Type	STANDARD SRAM
memory width	18
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	2.5/3.3 V
Certification status	Not Qualified
Maximum standby current	0.03 A
Minimum standby current	2.38 V
Maximum slew rate	0.28 mA
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

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0.13µm Process

ADVANCE

‡

36Mb: 2 MEG x 18, 1 MEG x 32/36

PIPELINED, SCD SYNCBURST SRAM

36Mb

SRAM

Features

SYNCBURST

™

MT58L2MY18P, MT58V2MV18P,

MT58L1MY32P, MT58V1MV32P,

MT58L1MY36P, MT58V1MV36P

3.3V V

, 3.3V or 2.5V I/O; 2.5V V

, 2.5V I/O

• Fast clock and OE# access times

• Single 3.3V ±5 percent or 2.5V ±5 percent power supply

• Separate 3.3V ±5 percent or 2.5V ±5 percent isolated

output buffer supply (V

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium® BSRAM-compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os, and control signals

• Internally self-timed WRITE cycle

• Automatic power-down

• Burst control (interleaved or linear burst)

• Low capacitive bus loading

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

Figure 2: 165-Ball FBGA

JEDEC-Standard MO-216 (Var. CAB-1)

Options

• Timing (Access/Cycle/MHz)

3.1ns/5ns/200 MHz

3.5ns/6ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

• Configurations

3.3V V

, 3.3V or 2.5V I/O

2 Meg x 18

1 Meg x 32

1 Meg x 36

2.5V V

, 2.5V I/O

2 Meg x 18

1 Meg x 32

1 Meg x 36

• Packages

100-pin, 16mm x 22.1mm TQFP

165-ball, 13mm x 15mm FBGA

TQFP

Marking

-5

-6

-7.5

-10

MT58L2MY18P

MT58L1MY32P

MT58L1MY36P

MT58V2MV18P

MT58V1MV32P

MT58V1MV36P

Part Number Example:

MT58L1MY36PT-10

General Description

The Micron® SyncBurst™ SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 36Mb SyncBurst SRAMs integrate a 2 Meg x

18, 1 Meg x 32, or 1 Meg x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

(CE#), two additional chip enables for easy depth

• Operating Temperature Range

Commercial (0ºC

+70ºC)

Industrial (-40ºC

+85ºC)

NOTE:

None

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact factory for availability of Industrial Temperature devices.

36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03

‡

PRODUCTS

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

0.13µm Process

ADVANCE

36Mb: 2 MEG x 18, 1 MEG x 32/36

PIPELINED, SCD SYNCBURST SRAM

Table 1:

SYMBOL

ADV#

TQFP Pin Descriptions

TYPE

Input

DESCRIPTION

Synchronous Address Advance: This active LOW input is used to advance the internal burst

counter, controlling burst access after the external address is loaded. A HIGH on this pin

effectively causes wait states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an

ADSP# cycle is initiated.

Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.

ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.

Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ or WRITE is performed using the

new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when

CE# is HIGH.

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be

written and must meet the setup and hold times around the rising edge of CLK. A byte write

enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36

versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc#

controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on

the x18 and x36 versions.

Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the

setup and hold times around the rising edge of CLK.

Synchronous Chip Enable: This active LOW input is used to enable the device and conditions

the internal use of ADSP#. CE# is sampled only when a new external address is loaded.

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded.

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded.

Clock: This signal registers the address, data, chip enable, byte write enables, and burst

control inputs on its rising edge. All synchronous inputs must meet setup and hold times

around the clock’s rising edge.

Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur

independent of the BWE# and BWx# lines and must meet the setup and hold times around

the rising edge of CLK.

Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or

HIGH on this pin selects “interleaved burst.” Do not alter input state while device is

operating. LBO# is the JEDEC-standard term for MODE.

Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is

the JEDEC-standard term for OE#.

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK.

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This pin has an internal pull-down and can be left unconnected.

SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is

associated with DQb pins. For the x32 and x36 versions, byte “a” is associated with DQa pins;

byte “b” is associated with DQb pins; byte “c” is associated with DQc pins; byte “d” is

associated with DQd pins. Input data must meet setup and hold times around the rising edge

of CLK.

ADSP#

Input

ADSC#

Input

BWa#

BWb#

BWc#

BWd#

Input

BWE#

CE#

CE2#

CE2

CLK

Input

GW#

Input

MODE

(LBO#)

OE# (G#)

SA0

SA1

Input

DQa

DQb

DQc

DQd

Input/

Output

36Mb: 2 Meg x 18, 1 Meg x 32/36, Pipelined, SCD SyncBurst SRAM

MT58L2MY18P1_16_B.fm - Rev. B, Pub 1/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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