M25PX64STVMF6TP datasheet, PDF

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M25PX64STVMF6TP: DescriptionEEPROM, 8MX8, Serial, CMOS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16; Categorystorage storage; File Size1MB，68 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com; Environmental Compliance

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M25PX64STVMF6TP Overview

EEPROM, 8MX8, Serial, CMOS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-16

M25PX64STVMF6TP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Numonyx ( Micron )
Parts packaging code	SOIC
package instruction	SOP, SOP16,.4
Contacts	16
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum clock frequency (fCLK)	75 MHz
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G16
length	10.3 mm
memory density	67108864 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	16
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.015 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
type	NOR TYPE
width	7.5 mm
Maximum write cycle time (tWC)	15 ms
write protect	HARDWARE/SOFTWARE

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M25PX64

64-Mbit, dual I/O, 4-Kbyte subsector erase,

serial flash memory with 75 MHz SPI bus interface

Preliminary Data

Features

SPI bus compatible serial interface

75 MHz (maximum) clock frequency

2.7 V to 3.6 V single supply voltage

Dual input/output instructions resulting in an

equivalent clock frequency of 150 MHz:

– Dual output fast read instruction

– Dual input fast program instruction

Whole memory continuously read by sending

once a fast read or a dual output fast read

instruction and an address

64 Mbit Flash memory

– Uniform 4-Kbyte subsectors

– Uniform 64-Kbyte sectors

Additional 64-byte user-lockable, one-time

programmable (OTP) area

Erase capability

– Subsector (4-Kbyte) granularity

– Sector (64-Kbyte) granularity

– Bulk erase (64 Mbits) in 68 s (typical)

Write protections

– Software write protection applicable to

every 64-Kbyte sector (volatile lock bit)

– Hardware write protection: protected area

size defined by three non-volatile bits (BP0,

BP1 and BP2)

Deep power-down mode: 5

μA

(typical)

Electronic signature

– JEDEC standard two-byte signature

(7117h)

– Unique ID code (UID) with 16 bytes read-

only, available upon customer request

More than 100 000 write cycles per sector

More than 20 years data retention

Packages

– RoHS compliant

VDFPN8 (ME)

8 × 6 mm (MLP8)

SO16 (MF)

300 mils width

TBGA 6x8 mm

February 2009

Rev 4

1/68

www.numonyx.com

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

Contents

M25PX64

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write protect/enhanced program supply voltage (W/V

) . . . . . . . . . . . . 10

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . 13

Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13

Active power, standby power and deep power-down modes . . . . . . . . . . 13

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.7.1

4.7.2

Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16

4.8

Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1

6.2

6.3

Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/68

M25PX64

Contents

6.4

Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Top/bottom bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

6.15

6.16

6.17

6.18

6.19

Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 37

Dual output fast read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read lock register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Dual input fast program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Write to lock register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Subsector erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3/68

List of tables

M25PX64

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Software protection truth table (sectors 0 to 127, 64-Kbyte granularity). . . . . . . . . . . . . . . 16

Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Lock register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Lock register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

VDFPN8 (MLP8) 8-lead very thin dual flat package no lead,

8 × 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 63

TBGA 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4/68

M25PX64

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 31

Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 33

Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 36

Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Dual output fast read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read lock register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . . 39

Read OTP (ROTP) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Page program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Dual input fast program (DIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Program OTP (POTP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

How to permanently lock the 64 OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Write to lock register (WRLR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Subsector erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 52

Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . . 60

Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

PPH

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

VDFPN8 (MLP8) 8-lead very thin dual flat package no lead,

8 × 6 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 63

TBGA, 6x8 mm, 24 ball package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5/68

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Some Problems with Differential Circuits: [i=s] This post was last edited by shaorc on 2019-3-21 09:56 [/i] [Ask if you don't understand] [color=#333333][font="][size=14px] [1] The differential circuit is shown in the figure below. They are b...; shaorc Analog electronics

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