Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5607B
Rev. 3, 01/2010
MPC5607B Microcontroller
Data Sheet
Features
•
Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture™
embedded category
— Enhanced instruction set allowing variable
length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed
16-bit and 32-bit instructions, it is possible to
achieve significant code size footprint
reduction.
Up to 1.5 Mbytes on-chip Flash supported with the
Flash controller
Up to 96 Kbytes on-chip SRAM
Memory protection unit (MPU) with 8 region
descriptors and 32-byte region granularity on certain
family members
Interrupt controller (INTC) capable of handling 204
selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, Flash, or RAM from multiple bus
masters
16-channel eDMA controller with multiple transfer
request sources using DMA multiplexer
Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
Timer supports I/O channels providing a range of
16-bit input capture, output compare, and pulse
width modulation functions (eMIOS)
2 analog-to-digital converters (ADC): one 10-bit and
one 12-bit
Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or PIT
176LQFP (24 x 24)
144 LQFP (20 x 20 )
208 MAPBGA (17 x 17
)
100 LQFP (14 x 14 )
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Up to 6 serial peripheral interface (DSPI) modules
Up to 10 serial communication interface (LINFlex)
modules
Up to 6 enhanced full CAN (FlexCAN) modules
with configurable buffers
1 inter-integrated circuit (I
2
C) interface module
Up to 149 configurable general purpose pins
supporting input and output operations (package
dependent)
Real-Time Counter (RTC)
— Clock source from internal 128 kHz or 16 MHz
oscillator supporting autonomous wakeup with
1 ms resolution with maximum timeout of 2
seconds
— Optional support for RTC with clock source
from external 32 kHz crystal oscillator,
supporting wakeup with 1 sec resolution and
maximum timeout of 1 hour
Up to 8 periodic interrupt timers (PIT) with 32-bit
counter resolution
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus
Device/board boundary scan testing supported per
Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
•
•
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
MPC5607B
Table of Contents
2
3
4
5
6
MPC5607B Microcontroller Data Sheet, Rev. 3
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
1
General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 176LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .8
2.2 144LQFP pin configuration . . . . . . . . . . . . . . . . . . . . . . .9
2.3 208MAPBGA pin configuration . . . . . . . . . . . . . . . . . . .10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .11
3.2.2 NVUSRO[OSCILLATOR_MARGIN] field
description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2.3 NVUSRO[WATCHDOG_EN] field description . .12
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .13
3.4 Recommended operating conditions . . . . . . . . . . . . . .14
3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .17
3.5.1 External ballast resistor recommendations . . . .17
3.5.2 Package thermal characteristics . . . . . . . . . . . .17
3.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .18
3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .18
3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .19
3.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .21
3.6.4 Output pin transition times . . . . . . . . . . . . . . . . .23
3.6.5 I/O pad current specification . . . . . . . . . . . . . . .24
3.7 nRSTIN electrical characteristics . . . . . . . . . . . . . . . . .27
3.8 Power management electrical characteristics. . . . . . . .30
3.8.1 Voltage regulator electrical characteristics . . . .30
3.8.2 Voltage monitor electrical characteristics. . . . . .33
3.9 Low voltage domain power consumption . . . . . . . . . . .35
3.10 Flash memory electrical characteristics . . . . . . . . . . . .37
3.10.1 Program/Erase characteristics. . . . . . . . . . . . . .37
3.10.2 Flash power supply DC characteristics . . . . . . .38
3.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 40
3.11 Electromagnetic compatibility (EMC) characteristics. . 40
3.11.1 Designing hardened software to avoid
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.2 Electromagnetic interference (EMI) . . . . . . . . . 41
3.11.3 Absolute maximum ratings (electrical sensitivity)41
3.12 Fast external crystal oscillator (4 to 16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.13 Slow external crystal oscillator (32 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 48
3.15 Fast internal RC oscillator (16 MHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.16 Slow internal RC oscillator (128 kHz)
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 50
3.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.17.2 Input impedance and ADC accuracy . . . . . . . . 51
3.17.3 ADC electrical characteristics . . . . . . . . . . . . . 56
3.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 64
3.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 66
3.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 73
3.18.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 74
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 75
4.1.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1.2 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.1.3 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1.4 208MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
General description
1
General description
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
The MPC5607B is a new family of next generation microcontrollers built on the Power Architecture™ embedded category.
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the device.
The MPC5607B family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It
belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics
applications within the vehicle. The advanced and cost-efficient host processor core of the MPC5607B automotive controller
family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding)
APU (Auxillary Processor Unit), providing improved code density. It operates at speeds of up to 64 MHz and offers high
performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of
current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist
with users implementations.
Table 1. MPC5607B Family Comparison
1
Feature
Package
CPU
Execution speed
3
Code Flash
Data Flash
RAM
MPU
DMA
10-bit ADC
dedicated
4
shared with 12-bit ADC
12-bit ADC
dedicated
5
shared with 10-bit ADC
Total timer I/O
6
eMIOS
Counter / OPWM / ICOC
7
O(I)PWM / OPWFMB /
OPWMCB / ICOC
8
O(I)PWM / ICOC
9
OPWM / ICOC
10
SCI (LINFlex)
SPI (DSPI)
CAN (FlexCAN)
7 ch
13 ch
4
3
6
5
8
6
6
5
6
37 ch,
16-bit
10 ch
7 ch
14 ch
33 ch
8
6
10
7 ch
15 ch
29 ch
64 KB
768 KB
100
LQFP
MPC5605B
144
LQFP
176
LQFP
MPC5606B
144
LQFP
e200z0h
Up to 64 MHz
1 MB
64 (4 x 16) Kbyte
80 KB
8-entry
16 ch
Yes
15 ch
19 ch
Yes
5 ch
19 ch
64 ch,
16-bit
29 ch
96 KB
1.5 MB
176
LQFP
MPC5607B
176
LQFP
208 MAP
BGA
2
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
General description
Table 1. MPC5607B Family Comparison
1
(continued)
Feature
I
2
C
32 kHz oscillator
GPIO
11
Debug
1
2
MPC5605B
MPC5606B
1
Yes
MPC5607B
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
77
121
149
JTAG
121
149
149
N2+
Feature set dependent on selected peripheral multiplexing; table shows example.
208 MAPBGA package is for debug use only.
3
Based on 105
°C
ambient operating temperature.
4
Not shared with 12-bit ADC, but possibly shared with other alternate functions.
5
Not shared with 10-bit ADC, but possibly shared with other alternate functions.
6
Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
7
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output
Compare.
8
Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output
Compare.
9
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and
Pulse width measurement.
10
Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
11
Maximum I/O count based on multiplexing with peripherals.
1.1
Block diagram
Figure 1
shows a top-level block diagram of the MPC5607B.
MPC5607B Microcontroller Data Sheet, Rev. 3
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
General description
JTAG
JTAG Port
Nexus Port
Nexus
NMI
SIUL
Voltage
Regulator
NMI
Interrupt requests
from peripheral
blocks
INTC
Clocks
FMPLL
CMU
eDMA
(Master)
Instructions
e200z0h
(Master)
Data
Nexus 2+
(Master)
RAM
96 KB
Code Flash DataFlash
1.5 MB
64 KB
SRAM
Controller
MPU
Flash
Controller
(Slave)
(Slave)
(Slave)
MPU
Registers
WKPU
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME MC_PCU
BAM
SSCM
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
External
Interrupt
Request
IMUX
GPIO &
Pad Control
19 ch 10bit/12bit 29 ch 10-bit
ADC
ADC
CTU
64 ch
eMIOS
10 x
LINFlex
6x
DSPI
I
2
C
6x
FlexCAN
I/O
Legend:
ADC
BAM
CAN
CMU
CTU
DSPI
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
LINFlex
MC_CGM
...
...
...
...
...
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network (FlexCAN)
Clock Monitor Unit
Cross Triggering Unit
Deserial Serial Peripheral Interface
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
Serial Communication Interface (LIN support)
Clock Generation Module
MC_ME
MPU
Nexus
NMI
MC_PCU
MC_RGM
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
Mode Entry Module
Memory Protection Unit
NexuS Development Interface (NDI) Level
Non-Maskable Interrupt
Power Control Unit
Reset Generation Module
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Figure 1. MPC5607B block diagram
MPC5607B Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
64-bit 2 x 3 Crossbar Switch
京公网安备 11010802033920号
EEWORLD
