IA
NT
Features
■
Formerly
■
■
■
■
■
■
Applications
■
POTS linecards
■
VolP equipment
■
Voice and data combo linecards
■
ONU, ONT
■
Gateways
■
Cable and DSL modems
brand
Extremely high speed performance
Blocks high voltages and currents
Two TBU
™
protectors in one small package
Simple, superior circuit protection
Minimal PCB area
RoHS compliant*, UL Recognized
*R
oH
S
CO
M
PL
TBU
™
P500-G and P850-G Protectors
Transient Blocking Units - TBU
™
Devices
Agency Approval
UL recognized component File # E315805.
Industry Standards
Description
Telcordia
ITU-T
GR-1089
Port Type 2, 4
Port Type 3, 5
Model
P500-G
P850-G
P850-G
Bourns
®
Model P500-G and P850-G
TBU
™
products are high speed, surge
protection components designed to
protect Subscriber Line Interface Circuits
(SLICs) against transients caused by
AC power cross, induction and lightning
surges.
The TBU device blocks surges and
provides an effective barrier behind
which sensitive electronics are not
exposed to large voltages or currents
during surge events.
™
K.20, K.20E, K.21, K.21E, K.45
Absolute Maximum Ratings (T
amb
= 25 °C)
Symbol
V
imp
V
rms
T
op
T
stg
Parameter
Maximum protection voltage for impulse faults with rise time
≥
1 µsec
Maximum protection voltage for continuous V
rms
faults
Operating temperature range
Storage temperature range
P500-Gxxx-WH
P850-Gxxx-WH
P500-Gxxx-WH
P850-Gxxx-WH
Value
500
850
300
425
-40 to +85
-65 to +150
Unit
V
V
°C
°C
Electrical Characteristics (T
amb
= 25 °C)
Symbol
Parameter
Maximum current through the device that will not cause
current blocking
P500-G120-WH
P500-G200-WH
P850-G120-WH
P850-G200-WH
P500-G120-WH
P500-G200-WH
P850-G120-WH
P850-G200-WH
P500-G120-WH
P500-G200-WH
P850-G120-WH
P850-G200-WH
50
150
275
150
275
200
400
200
400
55
2
1
0.7
22
Min.
Typ.
Max.
100
200
100
200
Unit
I
op
mA
I
trigger
Typical current for the device to go from normal operating
state to protected state
mA
I
out
Maximum current through the device
mA
Ω
Ω
µs
mA
V
R
TBU
R
bal
t
block
I
quiescent
V
reset
Series resistance of the TBU
™
device
Line-to line series resistance difference between two TBU
™
devices
Maximum time for the device to go from normal operating
state to protected state
Current through the triggered TBU
™
device with 50 Vdc circuit
voltage
Voltage below which the triggered TBU
™
device will transition to
normal operating state
The P-G series TBU
™
devices are bidirectional; specifications are valid in both directions.
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex.
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications
TBU
™
P500-G and P850-G Protectors
Typical Performance Characteristics
V-I Characteristics
+I
Time to Block vs. Fault Current
1
0.1
Itrigger
Time to Block (sec)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
0.1
1
10
100
1000
-Vreset
+V
Vreset
-Itrigger
Fault Current (A)
Trigger Current Temperature
140
120
% of Trigger Current
100
80
60
40
20
-40
-20
0
20
40
60
80
Temperature (°C)
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications
TBU
™
P500-G and P850-G Protectors
Operational Characteristics
The graphs below demonstrate the operational characteristics of the TBU
™
device. For each graph the fault voltage, protected side voltage,
and current is presented.
Tip
TEST CONFIGURATION DIAGRAM
Ring
Pxxx-G
P500-G Lightning, 500 V
P850-G Lightning, 850 V
3
Equipment
V1
V2
3
400 mA/div.
2
2
1
1
1 µs/div.
Ch1 V1
Ch2 V2
Ch3 Current
Ch1 V1
1
µ
s/div.
Ch2 V2
Ch3 Current
P500-G Power Fault, 120 Vrms, 25 A
P850-G Power Fault, 230 Vrms, 25 A
3
3
2
2
200 mA/div.
1
4 ms/div.
Ch1 V1
Ch2 V2
Ch3 Current
Ch1 V1
100 V/div.
1
4 ms/div.
Ch2 V2
Ch3 Current
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications
200 mA/div.
100 V/div.
200 mA/div.
100 V/div.
TBU
™
P500-G and P850-G Protectors
Product Dimensions
P500-Gxxx
J
B
C
E
K
K
F
J
E
N
Dim.
A
4
A
5
2
6
H
B
M
3
1
C
D
PIN 1
D
N
TOP VIEW
SIDE VIEW
K
J
BOTTOM VIEW
K
L
L
F
E
G
J
N
E
F
G
H
H H
P850-Gxxx
B
C
G
Min.
3.40
(.139)
5.90
(.232)
0.80
(.031)
0.000
(.000)
1.15
(.045)
1.05
(.041)
--
1.10
(.043)
0.375
(.015)
0.70
(.028)
--
0.70
(.028)
0.375
(.015)
P500-G
Typ.
4.00
(.157)
6.00
(.236)
0.85
(.033)
0.025
(.001)
1.25
(.049)
1.15
(.045)
--
1.20
(.047)
0.425
(.017)
0.75
(.030)
--
Max.
4.10
(.161)
6.10
(.240)
0.90
(.035)
0.050
(.002)
1.35
(.053)
1.25
(.049)
--
1.30
(.051)
0.475
(.019)
0.80
(.031)
--
E
4A
A
4
3
5
2
6
1
6A
1A
M
J
K
3A
PIN 1
D
N
L
M
N
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pads 1A and 1 are internally connected; the same for pads 3A with 3, 4A with 4, and 6A with 6.
This allows for one PCB layout to accommodate the P500 or P850.
0.75 0.80
(.030) (.031)
0.425 0.475
(.017) (.018)
DIMENSIONS:
P850-G
Min. Typ.
3.40 4.00
(.139) (.157)
8.15 8.25
(.321) (.325)
0.80 0.85
(.031) (.033)
0.000 0.025
(.000) (.001)
1.15 1.25
(.045) (.049)
1.05 1.15
(.041) (.045)
0.725 0.825
(.029) (.032)
1.10 1.20
(.043) (.047)
0.375 0.425
(.015) (.017)
0.25 0.30
(.010) (.012)
0.70 0.75
(.028) (.030)
0.70 0.75
(.028) (.030)
0.375 0.425
(.015) (.017)
MM
(INCHES)
Max.
4.10
(.161)
8.35
(.329)
0.90
(.035)
0.050
(.002)
1.35
(.053)
1.25
(.049)
0.925
(.036)
1.30
(.051)
0.475
(.019)
0.35
(.014)
0.80
(.031)
0.80
(.031)
0.475
(.018)
Recommended Pad Layout
P500-Gxxx
1.225
(.048) 1.275
(.050)
0.75
(.030)
1.15
(.045)
0.375
(.015)
Pad Designation
Pad #
Apply
1
Tip In
2
NC
3
Tip Out
4
Ring Out
5
NC
6
Ring In
NC = Solder to PCB; do not make electrical
connection, do not connect to ground.
Block Diagram
P500-Gxxx
6
4
1
3
P850-Gxxx
1.225
(.048)
0.85
(.033)
1.25
(.049)
1.15
(.045)
0.375
(.015)
0.30
(.012)
0.75
(.030)
Pad Designation
Pad #
Apply
Pad #
Apply
1A
Tip In
4A
Ring Out
1
Tip In
4
Ring Out
2
NC
5
NC
3
Tip Out
6
Ring In
3A
Tip Out
6A
Ring In
NC = Solder to PCB; do not make electrical
connection, do not connect to ground.
P850-Gxxx
6 & 6A
4 & 4A
1 & 1A
3 & 3A
TBU
™
devices have matte-tin termination finish. Suggested layout should use non-solder mask
define (NSMD). Recommended stencil thickness is 0.10-0.12 mm (.004-.005 in.) with stencil
opening size 0.025 mm (.0010 in.) less than the device pad size. As when heat sinking any power
device, it is recommended that, wherever possible, extra PCB copper area is allowed. For mini-
mum parasitic capacitance, do not allow any signal, ground or power signals beneath any of the
pads of the device.
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications
TBU
™
P500-G and P850-G Protectors
Thermal Resistances
Part #
P500-G
Symbol
R
th(j-a)
Parameter
Junction to leads (package)
Junction to leads (per TBU
™
device)
Junction to leads (package)
Junction to leads (per TBU
™
device)
Value
113
236
119
215
Unit
°C/W
°C/W
°C/W
°C/W
P850-G
R
th(j-a)
Reflow Profile
Profile Feature
Average Ramp-Up Rate (Tsmax to Tp)
Preheat
- Temperature Min. (Tsmin)
- Temperature Max. (Tsmax)
- Time (tsmin to tsmax)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5 °C of Actual Peak Temp. (tp)
Ramp-Down Rate
Time 25 °C to Peak Temperature
Pb-Free Assembly
3 °C/sec. max.
150 °C
200 °C
60-180 sec.
217 °C
60-150 sec.
260 °C
20-40 sec.
6 °C/sec. max.
8 min. max.
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications
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