V59C1G01408QBLP-3 datasheet, PDF

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V59C1G01408QBLP-3: Description256MX4 DDR DRAM, PBGA68, GREEN, FBGA-68; Categorystorage storage; File Size972KB，80 Pages; ManufacturerProMOS Technologies Inc

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V59C1G01408QBLP-3 Overview

256MX4 DDR DRAM, PBGA68, GREEN, FBGA-68

V59C1G01408QBLP-3 Parametric

Parameter Name	Attribute value
Maker	ProMOS Technologies Inc
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	68
Reach Compliance Code	unknown
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B68
length	13.65 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	68
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm

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V59C1G01(408/808)QB

HIGH PERFORMANCE 1Gbit DDR2 SDRAM

8 BANKS X 32Mbit X 4 (408)

8 BANKS X 16Mbit X 8 (808)

DDR2-533

Clock Cycle Time (t

CK3

)

Clock Cycle Time (t

CK4

)

Clock Cycle Time (t

CK5

)

Clock Cycle Time (t

CK6

)

Clock Cycle Time (t

CK7

)

System Frequency (f

CK max

)

5ns

3.75ns

266 MHz

DDR2-667

5ns

3.75ns

3ns

333 MHz

25A

DDR2-800

5ns

3.75ns

3ns

2.5ns

400 MHz

DDR2-800

5ns

3.75ns

2.5ns

400 MHz

19A

DDR2-1066

5ns

3.75ns

3ns

2.5ns

1.875ns

533 MHz

Features

■

High speed data transfer rates with system frequency

up to 533 MHz

■

8 internal banks for concurrent operation

■

4-bit prefetch architecture

■

Programmable CAS Latency: 3, 4 ,5 , 6 and 7

■

Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6

■

Write Latency=Read Latency-1

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length: 4 and 8

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase

between 0

C and 85

■

OCD (Off-Chip Driver Impendance Adjustment)

■

ODT (On-Die Termination)

■

Weak Strength Data-Output Driver Option

■

Bidirectional differential Data Strobe (Single-ended

data-strobe is an optional feature)

■

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■

DQS can be disabled for single-ended data strobe

■

Read Data Strobe (RDQS) supported (x8 only)

■

Differential clock inputs CK and CK

■

JEDEC Power Supply 1.8V ± 0.1V

■

VDDQ=1.8V ± 0.1V

■

Available in 68-ball FBGA

■

RoHS compliant

■

PASR Partial Array Self Refresh

■

tRAS lockout supported

Description

The V59C1G01(408/808)QB is a eight bank DDR

DRAM organized as 8 banks x 32Mbit x 4 (408), or 8 banks

x 16Mbit x 8 (808). The V59C1G01(408/808)QB achieves

high speed data transfer rates by employing a chip archi-

tecture that prefetches multiple bits and then synchroniz-

es the output data to a system clock.

The chip is designed to comply with the following key

DDR2 SDRAM features:(1) posted CAS with additive la-

tency, (2)write latency=read latency-1, (3)Off-chip Driver

(OCD) impedance adjustment, (4) On Die Termination.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

s are synchronized with a pair of bidirectional strobes

(DQS, DQS) in a source synchronous fashion.

Operating the eight memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Available Speed

Table 1:

Grade

-37 (DDR2-533)

-3 (DDR2-667)

-25A (DDR2-800)

-25 (DDR2-800)

-19A (DDR2-1066)

tRCD

tRP

Unit

CLK

Device Usage Chart

Operating

Temperature

Range

0°C to 85°C

-40°C to 85°C

V59C1G01(408/808)QB Rev.1.1 December 2008

Package Outline

68-ball FBGA

•

CK Cycle Time (ns)

-3

•

Power

Std.

•

-25A

•

-25

•

-19A

•

Temperature

Mark

Blank

ProMOS TECHNOLOGIES

Signal Pin Description

CKE

V59C1G01(408/808)QB

Type

Input

Function

The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.

Input

Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the

Power Down mode, or the Self Refresh mode.

CS enables the command decoder when low and disables the command decoder when high. When

the command decoder is disabled, new commands are ignored but previous operations continue.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be

executed by the SDRAM.

During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled

at the rising clock edge for x4 and x8 devices.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled

at the rising clock edge.CAn depends on the SDRAM organization:

128M x 4 DDR CAn = CA9, A11

64M x 8 DDR CAn = CA9

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of

the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1, BA2 defines the

bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0, BA1and BA2 to control

which bank(s) to precharge. If A10 is high, all eight banks will be precharged simultaneously regardless

of state of BA0 , BA1 and BA2.

Input

RAS, CAS WE

Input

A0 - A13

Input

BA0-BA2

DQx

LDQx

DQS,(DQS)

LDQS,(LDQS)

RDQS,(RDQS)

Input

Input/

Output

Input/

Output

Selects which bank is to be active.

Data Input/Output pins operate in the same manner as on conventional DRAMs.

DQ0-DQ3 for x4 component, DQ0-DQ7 for x8 component and LDQ0-LDQ7.

Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write

data. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing.

The data strobes DQS, LDQS, and RDQS may be used in single ended mode or paired with optional

complimentary signals DQS, LDQS, and RDQS to provide differential pair signaling to the system dur-

ing both reads and writes. AN EMRS(1) control bit enables or disables all complementary data strobe

signals.

In Write mode, DM operates as a word mask by allowing input data to be written if it is low but blocks

the write operation.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity. 1.8V +/- 0.1V

SSTL Reference Voltage for Inputs

Isolated power supply and ground for the DLL to provide improved noise

immunity. 1.8V +/- 0.1V

On Die Termination Enable. It enables termination resistance internal to the DRAM. ODT is applied to

each DQ, DQS, DQS and DM signals for x4 component and DQ, DQS, DQS, RDQS, RDQS and DM

for the x8 component. ODT will be ignored if EMRS disable the function.

Reserved for future use

DM,

LDM,UDM

VDD,VSS

VDDQ VSSQ

Input

Supply

VREF

VDDLQ VSSDL

Input

Supply

ODT

Input

RFU

V59C1G01(408/808)QB Rev. 1.1 December 2008

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