K4T51043QG-HCLCC datasheet, PDF

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K4T51043QG-HCLCC: Description512Mb G-die DDR2 SDRAM Specification; File Size999KB，47 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4T51043QG-HCLCC Overview

512Mb G-die DDR2 SDRAM Specification

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K4T51043QG

K4T51083QG

K4T51163QG

DDR2 SDRAM

512Mb G-die DDR2 SDRAM Specification

60FBGA & 84FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 47

Rev. 1.4 December 2008

K4T51043QG

K4T51083QG

K4T51163QG

DDR2 SDRAM

Table of Contents

1.0 Ordering Information ....................................................................................................................4

2.0 Key Features .................................................................................................................................4

3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5

3.1 x4 package pinout (Top View) : 60ball FBGA Package

.........................................................................5

3.2 x8 package pinout (Top View) : 60ball FBGA Package

.........................................................................6

3.3 x16 package pinout (Top View) : 84ball FBGA Package

.......................................................................7

3.4 FBGA Package Dimension(x4/ x8)

....................................................................................................8

3.5 FBGA Package Dimension(x16)

.......................................................................................................9

4.0 Input/Output Functional Description ........................................................................................10

5.0 DDR2 SDRAM Addressing .........................................................................................................11

6.0 Absolute Maximum DC Ratings .................................................................................................12

7.0 AC & DC Operating Conditions .................................................................................................12

.......................................................................12

7.2 Operating Temperature Condition

..................................................................................................13

7.3 Input DC Logic Level

....................................................................................................................13

7.4 Input AC Logic Level

....................................................................................................................13

7.5 AC Input Test Conditions

..............................................................................................................13

7.6 Differential input AC logic Level

.....................................................................................................14

7.7 Differential AC output parameters

..................................................................................................14

8.0 ODT DC electrical characteristics .............................................................................................14

9.0 OCD default characteristics ......................................................................................................15

10.0 IDD Specification Parameters and Test Conditions ..............................................................16

11.0 DDR2 SDRAM IDD Spec ...........................................................................................................18

12.0 Input/Output capacitance .........................................................................................................19

13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................19

13.1 Refresh Parameters by Device Density

........................................................................................19

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

.............................................19

13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)

........................................................20

13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)

........................................................22

14.0 General notes, which may apply for all AC parameters ........................................................24

15.0 Specific Notes for dedicated AC parameters .........................................................................26

7.1 Recommended DC Operating Conditions (SSTL - 1.8)

2 of 47

Rev. 1.4 December 2008

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