FPGA+PCI9054 data acquisition card

zxm1943918841

FPGA+PCI9054 data acquisition card [Copy link]

I bought an FPGA+pci9054 data acquisition card and collected AD data on the PC. The console program was in the VC++6.0 environment. When I added a loop to the main program in VC++6.0 and hoped to realize multiple data collection, I tested the time of one loop, which was about 100ms. Why was it so long? I hope you can help me. Supplementary content (2018-10-11 16:08): Later, I changed the AD module in the FPGA, and the collection time became 15ms/time. PCI9054 worked in the slave mode of C mode and used IO transmission. This is the FPGA program: always@(posedge LCLK) begin if(!RST_N) state<=s0; else state<=n_state; end Supplementary content (2018-10-11 16:10): always@( state or RST_N or ADS_N or LHOLD or LWDRD_N or BLAST_N ) begin if(!RST_N) n_state=s0; else case(state) s0: if(!ADS_N) n_state=s1; else n_state=s0; Supplementary content (2018-10-11 16:11): s1: if(!BLAST_N) n_state=s2; else n_state=s1; s2: n_state=s3; s3: if( ADS_N && BLAST_N ) n_state = s0; else if (!ADS_N) n_state = s1; Supplementary content (2018-10-11 16:11): else n_state = s3; default: n_state =s0; endcase end Supplementary content (2018-10-11 16:11): always@( state or RST_N or ADS_N or LHOLD or LWDRD_N or BLAST_N ) begin if(!RST_N) begin iready_n=1'b1; ienable_n=1'b1; end 补充内容(2018-10-11 16:12): else case(state) s0: begin iready_n=1'b1; ienable_n=1'b1; end s1: begin iready_n=1'b1; ienable_n=1'b0; end s2: begin iready_n=1'b0; 补充内容(2018-10-11 16:12): ienable_n=1'b0; end s3: begin iready_n=1'b1; ienable_n=1'b1; end default: begin iready_n=1'b1; ienable_n=1'b1; end endcase end Additional content (2018-10-11 16:12): always@(posedge LCLK) begin if(!RST_N) LHOLDA <= 1'b0; else begin if (LHOLD) LHOLDA <= 1'b1; else LHOLDA <= 1'b0; end end endmodule Additional content (2018-10-11 16:13): This is the state machine in the FPGA Additional content (2018-10-19 16:26): PCI9054 works in the slave mode of C mode and uses IO transmission to collect eight data from the FPGA at a time, but the collection speed is very slow. The following is the data collected by signaltap: Why does the first data collection time in the collection process take so long? And I set the collection on the PC to be cyclic, but it shows here...

testset

FPGA state machine is too simple?

竹叶听筝

What did you write your driver in?