DATA SHEET
8G bits DDR3 SDRAM, DDP
EDJ8232B5MB (256M words
32 bits)
Specifications
Density: 8G bits
Organization
32M words
32 bits
8 banks
Package
136-ball FBGA
DDP: 2 pieces of 4G bits chip sealed in one
package
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ
½
1.5V
0.075V
Data rate
1600Mbps/1333Mbps (max.)
4KB page size
Row address: A0 to A14
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS Write Latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8s at 0C
TC
85C
3.9s at
85C
TC
95C
Operating case temperature range
TC = 0C to +95C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1825E30 (Ver. 3.0)
Date Published March 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2011-2012
EDJ8232B5MB
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Block Diagram (DDP) ....................................................................................................................................4
Electrical Conditions ......................................................................................................................................7
Absolute Maximum Ratings .........................................................................................................................7
Operating Temperature Condition ...............................................................................................................7
Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V) ..................8
AC and DC Input Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V)......................8
VREF Tolerances ...................................................................................................................................... 10
Input Slew Rate Derating ........................................................................................................................... 11
AC and DC Logic Input Levels for Differential Signals ............................................................................... 16
AC and DC Output Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V) ................. 21
AC Overshoot/Undershoot Specification.................................................................................................... 23
Output Driver Impedance........................................................................................................................... 24
On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................26
ODT Timing Definitions.............................................................................................................................. 28
IDD Measurement Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V) .................................. 32
Electrical Specifications...............................................................................................................................45
DC Characteristics 1 (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V) ................................................ 45
Pin Capacitance (TC = 25C, VDD, VDDQ = 1.5V
0.075V) .................................................................... 47
Standard Speed Bins ................................................................................................................................. 48
AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.5V
0.075V, VSS, VSSQ = 0V)...................... 50
Block Diagram (Chip) ..................................................................................................................................58
Pin Function.................................................................................................................................................59
Command Operation ...................................................................................................................................61
Command Truth Table ............................................................................................................................... 61
CKE Truth Table ........................................................................................................................................ 65
Simplified State Diagram .............................................................................................................................66
RESET and Initialization Procedure ............................................................................................................67
Power-Up and Initialization Sequence ....................................................................................................... 67
Reset and Initialization with Stable Power ................................................................................................. 68
Programming the Mode Register.................................................................................................................69
Mode Register Set Command Cycle Time (tMRD) ....................................................................................69
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 69
DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 70
DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 71
Data Sheet E1825E30 (Ver. 3.0)
5
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