EDJ8232B5MB-DJ-F datasheet, PDF

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EDJ8232B5MB-DJ-F: Description8G bits DDR3 SDRAM, DDP; Categorystorage storage; File Size1MB，142 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EDJ8232B5MB-DJ-F Overview

8G bits DDR3 SDRAM, DDP

EDJ8232B5MB-DJ-F Parametric

Parameter Name	Attribute value
Maker	ELPIDA
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	136
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B136
JESD-609 code	e1
length	14 mm
memory density	8589934592 bi
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	136
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX32
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	10.5 mm

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DATA SHEET

8G bits DDR3 SDRAM, DDP

EDJ8232B5MB (256M words



32 bits)

Specifications



Density: 8G bits



Organization



32M words



32 bits



8 banks



Package



136-ball FBGA



DDP: 2 pieces of 4G bits chip sealed in one

package



Lead-free (RoHS compliant) and Halogen-free



Power supply: VDD, VDDQ

1.5V



0.075V



Data rate



1600Mbps/1333Mbps (max.)



4KB page size



Row address: A0 to A14



Column address: A0 to A9



Eight internal banks for concurrent operation



Interface: SSTL_15



Burst lengths (BL): 8 and 4 with Burst Chop (BC)



Burst type (BT):



Sequential (8, 4 with BC)



Interleave (8, 4 with BC)



/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11



/CAS Write Latency (CWL): 5, 6, 7, 8



Precharge: auto precharge option for each burst

access



Driver strength: RZQ/7, RZQ/6 (RZQ = 240)



Refresh: auto-refresh, self-refresh



Refresh cycles



Average refresh period

7.8s at 0C



 85C

3.9s at

85C 

 95C



Operating case temperature range



TC = 0C to +95C

Features



Double-data-rate architecture: two data transfers per

clock cycle



The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture



Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver



DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs



Differential clock inputs (CK and /CK)



DLL aligns DQ and DQS transitions with CK

transitions



Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS



Data mask (DM) for write data



Posted /CAS by programmable additive latency for

better command and data bus efficiency



On-Die Termination (ODT) for better signal quality



Synchronous ODT



Dynamic ODT



Asynchronous ODT



Multi Purpose Register (MPR) for pre-defined pattern

read out



ZQ calibration for DQ drive and ODT



Programmable Partial Array Self-Refresh (PASR)



/RESET pin for Power-up sequence and reset

function



SRT range:



Normal/extended



Programmable Output driver impedance control

Document No. E1825E30 (Ver. 3.0)

Date Published March 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2011-2012

EDJ8232B5MB

CONTENTS

Specifications.................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Block Diagram (DDP) ....................................................................................................................................4

Electrical Conditions ......................................................................................................................................7

Absolute Maximum Ratings .........................................................................................................................7

Operating Temperature Condition ...............................................................................................................7

Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V) ..................8

AC and DC Input Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V)......................8

VREF Tolerances ...................................................................................................................................... 10

Input Slew Rate Derating ........................................................................................................................... 11

AC and DC Logic Input Levels for Differential Signals ............................................................................... 16

AC and DC Output Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V) ................. 21

AC Overshoot/Undershoot Specification.................................................................................................... 23

Output Driver Impedance........................................................................................................................... 24

On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................26

ODT Timing Definitions.............................................................................................................................. 28

IDD Measurement Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V) .................................. 32

Electrical Specifications...............................................................................................................................45

DC Characteristics 1 (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V) ................................................ 45

Pin Capacitance (TC = 25C, VDD, VDDQ = 1.5V



0.075V) .................................................................... 47

Standard Speed Bins ................................................................................................................................. 48

AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.5V



0.075V, VSS, VSSQ = 0V)...................... 50

Block Diagram (Chip) ..................................................................................................................................58

Pin Function.................................................................................................................................................59

Command Operation ...................................................................................................................................61

Command Truth Table ............................................................................................................................... 61

CKE Truth Table ........................................................................................................................................ 65

Simplified State Diagram .............................................................................................................................66

RESET and Initialization Procedure ............................................................................................................67

Power-Up and Initialization Sequence ....................................................................................................... 67

Reset and Initialization with Stable Power ................................................................................................. 68

Programming the Mode Register.................................................................................................................69

Mode Register Set Command Cycle Time (tMRD) ....................................................................................69

MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 69

DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 70

DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 71

Data Sheet E1825E30 (Ver. 3.0)

EDJ8232B5MB-DJ-F Related Products

	EDJ8232B5MB-DJ-F	EDJ8232B5MB	EDJ8232B5MB-GN-F
Description	8G bits DDR3 SDRAM, DDP	8G bits DDR3 SDRAM, DDP	8G bits DDR3 SDRAM, DDP
Maker	ELPIDA	-	ELPIDA
Parts packaging code	BGA	-	BGA
package instruction	TFBGA,	-	TFBGA,
Contacts	136	-	136
Reach Compliance Code	unknow	-	unknown
ECCN code	EAR99	-	EAR99
access mode	MULTI BANK PAGE BURST	-	MULTI BANK PAGE BURST
Maximum access time	0.255 ns	-	0.225 ns
Other features	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B136	-	R-PBGA-B136
JESD-609 code	e1	-	e1
length	14 mm	-	14 mm
memory density	8589934592 bi	-	8589934592 bit
Memory IC Type	DDR DRAM	-	DDR DRAM
memory width	32	-	32
Number of functions	1	-	1
Number of ports	1	-	1
Number of terminals	136	-	136
word count	268435456 words	-	268435456 words
character code	256000000	-	256000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS
Maximum operating temperature	85 °C	-	85 °C
organize	256MX32	-	256MX32
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TFBGA	-	TFBGA
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height	1.2 mm	-	1.2 mm
self refresh	YES	-	YES
Maximum supply voltage (Vsup)	1.575 V	-	1.575 V
Minimum supply voltage (Vsup)	1.425 V	-	1.425 V
Nominal supply voltage (Vsup)	1.5 V	-	1.5 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	OTHER	-	OTHER
Terminal surface	TIN SILVER COPPER	-	TIN SILVER COPPER
Terminal form	BALL	-	BALL
Terminal pitch	0.8 mm	-	0.8 mm
Terminal location	BOTTOM	-	BOTTOM
width	10.5 mm	-	10.5 mm

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