W3HG2128M72AEF665F2MAG datasheet, PDF

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W3HG2128M72AEF665F2MAG: DescriptionDDR DRAM Module, 256MX72, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size349KB，18 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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W3HG2128M72AEF665F2MAG Overview

DDR DRAM Module, 256MX72, CMOS, ROHS COMPLIANT, DIMM-240

W3HG2128M72AEF665F2MAG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1716446509
package instruction	,
Reach Compliance Code	unknown
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240
JESD-609 code	e4
memory density	19327352832 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	256MX72
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal surface	GOLD
Terminal form	NO LEAD
Terminal location	DUAL

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White Electronic Designs

W3HG2128M72AEF-Fx

ADVANCED*

2GB – 2x128Mx72 DDR2 SDRAM FBDIMM, ECC

FEATURES

240-pin DDR2 fully buffered, dual in-line memory

module (FBDIMM) with ECC to detect and report

channel errors to the host memory controller.

Fast DDR2 DRAM data transfer rates: PC2-6400*,

PC2-5300, and PC2-4300

3.2 Gb/s and 4.0 Gb link transfer rates

High speed differential point-to-point link between

host memory controller and the AMB using serial,

dual-simplex bit lanes

• 10-pair southbound (data path to FBDIMM)

• 14-pair northbound (data path to FBDIMM)

Fault tolerant; can work around a bad bit lane in

each direction

High density scaling with up to 8 dual-rank modules

(288 DDR2 SDRAM devices) per channel

SMBus interface to AMB for conﬁguration register

access.

In-band and out-bank command access

Deterministic protocol

• Enables memory controller to optimize DRAM

access for maximum performance

• Delivers precise control and repeatable memory

behavior

Automatic DDR2 SDRAM bus and channel

calibration

Transmitter de-emphasis to reduce ISI

MBIST and IBIST test functions

Transparent mode for DDR2 SDRAM test support

= V

CCQ

= +1.8V for DDR2 SDRAM

REF

= 0.9V SDRAM C/A termination

= 1.5V for advanced memory buffer (AMB)

Serial Presence Detect (SPD) with EEPROM

Gold edge contacts

Dual rank

RoHS

DESCRIPTION

The W3HG2128M72AEF is a 2x128Mx72 fully buffered

240-pin Double Data Rate 2 SDRAM memory module

based on 512Mb DDR2 SDRAM components. The module

consists of thirty six 128Mx4, in FBGA package and a AMB

mounted on a 240 pin FR4 substrate.

* This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

NOTE: Consult factory for availability of:

• Vendor source control options

PERFORMANCE PARAMETERS

Speed Grade

665

534

Module Bandwidth

PC2-5300

PC2-4200

Peak Channel Throughput

8.0 GB/s

6.4 GB/s

Link Transfer Rate

4.0 GT/s

3.2 GT/s

Latency (CL-t

RCD

-t

)

5-5-5

4-4-4

* Consult factory for availability

Note: JEDEC has not yet adopted a

ﬁ

nal FBDIMM standard

June 2007

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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