MT57V2MH18EF-7.5 datasheet, PDF

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MT57V2MH18EF-7.5: DescriptionDDR SRAM, 2MX18, 3.6ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size321KB，24 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT57V2MH18EF-7.5 Overview

DDR SRAM, 2MX18, 3.6ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

MT57V2MH18EF-7.5 Parametric

Parameter Name	Attribute value
Maker	Micron Technology
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.6 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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Die Revision A

ADVANCE

‡

2 MEG x 18, 1 MEG x 36

2.5V V

, HSTL, Pipelined DDRb4 SRAM

36Mb DDR SRAM

4-Word Burst

Features

•

Fast cycle times

Pipelined, double data rate operation

Single 2.5V ±0.1V power supply (V

)

Separate isolated output buffer 1.5V to 1.8V (±0.1V)

supply (V

JEDEC-standard HSTL I/O

User-selectable trip point with V

REF

HSTL programmable impedance outputs

synchronized to optional dual-data clocks

Echo clock outputs

JTAG boundary scan

Fully-static design for reduced-power standby

Clock-stop capability

Common data inputs and data outputs

Low-control ball count

Internally self-timed, registered LATE WRITE cycles

Linear burst order with four-tick burst counter

15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA

package

Full data coherency, providing most current data

MT57V2MH18E

MT57V1MH36E

Figure 1: 165-Ball FBGA

Table 1:

Valid Part Numbers

DESCRIPTION

2 Meg x 18, DDR, Pipelined SRAM

1 Meg x 36, DDR, Pipelined SRAM

PART NUMBER

MT57V2MH18EF-xx

MT57V1MH36EF-xx

General Description

Options

• Clock Cycle Timing

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

• Configurations

2 Meg x 18

1 Meg x 36

• Operating Temperature Range

• Commercial (0°C

70°C)

• Package

165-ball, 15mm x 17mm FBGA

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

Marking

-5

-6

-7.5

MT57V2MH18E

MT57V1MH36E

None

The Micron

DDR synchronous SRAM employs

high-speed, low-power CMOS designs using an

advanced 6T CMOS process.

The DDR SRAM integrates a 36Mb SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active LOW load (LD#) and read/write (R/W#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K#, if C

and C# are not provided.

Asynchronous inputs include impedance match

(ZQ). Synchronous data outputs (Q) are closely

matched to the two echo clocks (CQ and CQ#), which

can be used as data receive clocks. Output data clocks

(C, C#) are also provided for maximum system clock-

ing and data synchronization flexibility.

36Mb: 2.5V V

, HSTL, Pipelined DDRb2 SRAM

MT57V2MH18E_13_A.fm - Rev. A, Pub. 1/03

‡

PRODUCTS

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

MT57V2MH18EF-7.5 Related Products

	MT57V2MH18EF-7.5	MT57V2MH18EF-5	MT57V2MH18EF-6	MT57V1MH36EF-7.5
Description	DDR SRAM, 2MX18, 3.6ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 2MX18, 2.4ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 2MX18, 3ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165	DDR SRAM, 1MX36, 3.6ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	TBGA,	TBGA,	TBGA,	TBGA,
Contacts	165	165	165	165
Reach Compliance Code	unknown	unknown	unknown	unknow
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3.6 ns	2.4 ns	3 ns	3.6 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e1	e1	e1	e1
length	17 mm	17 mm	17 mm	17 mm
memory density	37748736 bit	37748736 bit	37748736 bit	37748736 bi
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	18	18	36
Number of functions	1	1	1	1
Number of terminals	165	165	165	165
word count	2097152 words	2097152 words	2097152 words	1048576 words
character code	2000000	2000000	2000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	2MX18	2MX18	2MX18	1MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA	TBGA	TBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V
Minimum supply voltage (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	15 mm	15 mm	15 mm	15 mm
Maker	Micron Technology	-	Micron Technology	Micron Technology

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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