NAND Gate, TTL, PDIP14
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Philips Semiconductors (NXP Semiconductors N.V.) |
| package instruction | DIP, DIP14,.3 |
| Reach Compliance Code | unknown |
| JESD-30 code | R-PDIP-T14 |
| JESD-609 code | e0 |
| Logic integrated circuit type | NAND GATE |
| MaximumI(ol) | 0.024 A |
| Number of terminals | 14 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output characteristics | OPEN-COLLECTOR |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP14,.3 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| power supply | 5 V |
| Maximum supply current (ICC) | 12 mA |
| Prop。Delay @ Nom-Sup | 32 ns |
| Schmitt trigger | NO |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | TTL |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
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